0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner R40 TCON TOP Device Tree Bindings
0008
0009 maintainers:
0010 - Chen-Yu Tsai <wens@csie.org>
0011 - Maxime Ripard <mripard@kernel.org>
0012
0013 description: |
0014 TCON TOPs main purpose is to configure whole display pipeline. It
0015 determines relationships between mixers and TCONs, selects source
0016 TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV
0017 encoder clock source and contains additional TV TCON and DSI gates.
0018
0019 It allows display pipeline to be configured in very different ways:
0020
0021 / LCD0/LVDS0
0022 / [0] TCON-LCD0
0023 | \ MIPI DSI
0024 mixer0 |
0025 \ / [1] TCON-LCD1 - LCD1/LVDS1
0026 TCON-TOP
0027 / \ [2] TCON-TV0 [0] - TVE0/RGB
0028 mixer1 | \
0029 | TCON-TOP - HDMI
0030 | /
0031 \ [3] TCON-TV1 [1] - TVE1/RGB
0032
0033 Note that both TCON TOP references same physical unit. Both mixers
0034 can be connected to any TCON. Not all TCON TOP variants support all
0035 features.
0036
0037 properties:
0038 "#clock-cells":
0039 const: 1
0040
0041 compatible:
0042 enum:
0043 - allwinner,sun8i-r40-tcon-top
0044 - allwinner,sun20i-d1-tcon-top
0045 - allwinner,sun50i-h6-tcon-top
0046
0047 reg:
0048 maxItems: 1
0049
0050 clocks:
0051 minItems: 2
0052 maxItems: 6
0053
0054 clock-names:
0055 minItems: 2
0056 maxItems: 6
0057
0058 clock-output-names:
0059 minItems: 1
0060 maxItems: 3
0061
0062 resets:
0063 maxItems: 1
0064
0065 ports:
0066 $ref: /schemas/graph.yaml#/properties/ports
0067
0068 properties:
0069 port@0:
0070 $ref: /schemas/graph.yaml#/properties/port
0071 description: |
0072 Input endpoint for Mixer 0 mux.
0073
0074 port@1:
0075 $ref: /schemas/graph.yaml#/properties/port
0076 description: |
0077 Output endpoint for Mixer 0 mux
0078
0079 port@2:
0080 $ref: /schemas/graph.yaml#/properties/port
0081 description: |
0082 Input endpoint for Mixer 1 mux.
0083
0084 port@3:
0085 $ref: /schemas/graph.yaml#/properties/port
0086 description: |
0087 Output endpoint for Mixer 1 mux
0088
0089 port@4:
0090 $ref: /schemas/graph.yaml#/properties/port
0091 description: |
0092 Input endpoint for HDMI mux.
0093
0094 port@5:
0095 $ref: /schemas/graph.yaml#/properties/port
0096 description: |
0097 Output endpoint for HDMI mux
0098
0099 required:
0100 - port@0
0101 - port@1
0102 - port@4
0103 - port@5
0104
0105 required:
0106 - "#clock-cells"
0107 - compatible
0108 - reg
0109 - clocks
0110 - clock-names
0111 - clock-output-names
0112 - resets
0113 - ports
0114
0115 additionalProperties: false
0116
0117 allOf:
0118 - if:
0119 properties:
0120 compatible:
0121 contains:
0122 const: allwinner,sun8i-r40-tcon-top
0123
0124 then:
0125 properties:
0126 clocks:
0127 items:
0128 - description: The TCON TOP interface clock
0129 - description: The TCON TOP TV0 clock
0130 - description: The TCON TOP TVE0 clock
0131 - description: The TCON TOP TV1 clock
0132 - description: The TCON TOP TVE1 clock
0133 - description: The TCON TOP MIPI DSI clock
0134
0135 clock-names:
0136 items:
0137 - const: bus
0138 - const: tcon-tv0
0139 - const: tve0
0140 - const: tcon-tv1
0141 - const: tve1
0142 - const: dsi
0143
0144 clock-output-names:
0145 items:
0146 - description: TCON TV0 output clock name
0147 - description: TCON TV1 output clock name
0148 - description: DSI output clock name
0149
0150 ports:
0151 required:
0152 - port@2
0153 - port@3
0154
0155 - if:
0156 properties:
0157 compatible:
0158 contains:
0159 const: allwinner,sun20i-d1-tcon-top
0160
0161 then:
0162 properties:
0163 clocks:
0164 items:
0165 - description: The TCON TOP interface clock
0166 - description: The TCON TOP TV0 clock
0167 - description: The TCON TOP TVE0 clock
0168 - description: The TCON TOP MIPI DSI clock
0169
0170 clock-names:
0171 items:
0172 - const: bus
0173 - const: tcon-tv0
0174 - const: tve0
0175 - const: dsi
0176
0177 clock-output-names:
0178 items:
0179 - description: TCON TV0 output clock name
0180 - description: DSI output clock name
0181
0182 - if:
0183 properties:
0184 compatible:
0185 contains:
0186 const: allwinner,sun50i-h6-tcon-top
0187
0188 then:
0189 properties:
0190 clocks:
0191 items:
0192 - description: The TCON TOP interface clock
0193 - description: The TCON TOP TV0 clock
0194
0195 clock-names:
0196 items:
0197 - const: bus
0198 - const: tcon-tv0
0199
0200 clock-output-names:
0201 items:
0202 - description: TCON TV0 output clock name
0203
0204 examples:
0205 - |
0206 #include <dt-bindings/interrupt-controller/arm-gic.h>
0207
0208 #include <dt-bindings/clock/sun8i-r40-ccu.h>
0209 #include <dt-bindings/reset/sun8i-r40-ccu.h>
0210
0211 tcon_top: tcon-top@1c70000 {
0212 compatible = "allwinner,sun8i-r40-tcon-top";
0213 reg = <0x01c70000 0x1000>;
0214 clocks = <&ccu CLK_BUS_TCON_TOP>,
0215 <&ccu CLK_TCON_TV0>,
0216 <&ccu CLK_TVE0>,
0217 <&ccu CLK_TCON_TV1>,
0218 <&ccu CLK_TVE1>,
0219 <&ccu CLK_DSI_DPHY>;
0220 clock-names = "bus",
0221 "tcon-tv0",
0222 "tve0",
0223 "tcon-tv1",
0224 "tve1",
0225 "dsi";
0226 clock-output-names = "tcon-top-tv0",
0227 "tcon-top-tv1",
0228 "tcon-top-dsi";
0229 resets = <&ccu RST_BUS_TCON_TOP>;
0230 #clock-cells = <1>;
0231
0232 ports {
0233 #address-cells = <1>;
0234 #size-cells = <0>;
0235
0236 tcon_top_mixer0_in: port@0 {
0237 reg = <0>;
0238
0239 tcon_top_mixer0_in_mixer0: endpoint {
0240 remote-endpoint = <&mixer0_out_tcon_top>;
0241 };
0242 };
0243
0244 tcon_top_mixer0_out: port@1 {
0245 #address-cells = <1>;
0246 #size-cells = <0>;
0247 reg = <1>;
0248
0249 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
0250 reg = <0>;
0251 };
0252
0253 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
0254 reg = <1>;
0255 };
0256
0257 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
0258 reg = <2>;
0259 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
0260 };
0261
0262 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
0263 reg = <3>;
0264 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
0265 };
0266 };
0267
0268 tcon_top_mixer1_in: port@2 {
0269 #address-cells = <1>;
0270 #size-cells = <0>;
0271 reg = <2>;
0272
0273 tcon_top_mixer1_in_mixer1: endpoint@1 {
0274 reg = <1>;
0275 remote-endpoint = <&mixer1_out_tcon_top>;
0276 };
0277 };
0278
0279 tcon_top_mixer1_out: port@3 {
0280 #address-cells = <1>;
0281 #size-cells = <0>;
0282 reg = <3>;
0283
0284 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
0285 reg = <0>;
0286 };
0287
0288 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
0289 reg = <1>;
0290 };
0291
0292 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
0293 reg = <2>;
0294 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
0295 };
0296
0297 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
0298 reg = <3>;
0299 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
0300 };
0301 };
0302
0303 tcon_top_hdmi_in: port@4 {
0304 #address-cells = <1>;
0305 #size-cells = <0>;
0306 reg = <4>;
0307
0308 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
0309 reg = <0>;
0310 remote-endpoint = <&tcon_tv0_out_tcon_top>;
0311 };
0312
0313 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
0314 reg = <1>;
0315 remote-endpoint = <&tcon_tv1_out_tcon_top>;
0316 };
0317 };
0318
0319 tcon_top_hdmi_out: port@5 {
0320 reg = <5>;
0321
0322 tcon_top_hdmi_out_hdmi: endpoint {
0323 remote-endpoint = <&hdmi_in_tcon_top>;
0324 };
0325 };
0326 };
0327 };
0328
0329 ...
