0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings
0008
0009 description: |
0010 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
0011 IP with Allwinner\'s own PHY IP. It supports audio and video outputs
0012 and CEC.
0013
0014 These DT bindings follow the Synopsys DWC HDMI TX bindings defined
0015 in bridge/synopsys,dw-hdmi.yaml with the following device-specific
0016 properties.
0017
0018 maintainers:
0019 - Chen-Yu Tsai <wens@csie.org>
0020 - Maxime Ripard <mripard@kernel.org>
0021
0022 properties:
0023 "#phy-cells":
0024 const: 0
0025
0026 compatible:
0027 oneOf:
0028 - const: allwinner,sun8i-a83t-dw-hdmi
0029 - const: allwinner,sun50i-h6-dw-hdmi
0030
0031 - items:
0032 - enum:
0033 - allwinner,sun8i-h3-dw-hdmi
0034 - allwinner,sun8i-r40-dw-hdmi
0035 - allwinner,sun50i-a64-dw-hdmi
0036 - const: allwinner,sun8i-a83t-dw-hdmi
0037
0038 reg:
0039 maxItems: 1
0040
0041 reg-io-width:
0042 const: 1
0043
0044 interrupts:
0045 maxItems: 1
0046
0047 clocks:
0048 minItems: 3
0049 items:
0050 - description: Bus Clock
0051 - description: Register Clock
0052 - description: TMDS Clock
0053 - description: HDMI CEC Clock
0054 - description: HDCP Clock
0055 - description: HDCP Bus Clock
0056
0057 clock-names:
0058 minItems: 3
0059 items:
0060 - const: iahb
0061 - const: isfr
0062 - const: tmds
0063 - const: cec
0064 - const: hdcp
0065 - const: hdcp-bus
0066
0067 resets:
0068 minItems: 1
0069 items:
0070 - description: HDMI Controller Reset
0071 - description: HDCP Reset
0072
0073 reset-names:
0074 minItems: 1
0075 items:
0076 - const: ctrl
0077 - const: hdcp
0078
0079 phys:
0080 maxItems: 1
0081 description:
0082 Phandle to the DWC HDMI PHY.
0083
0084 phy-names:
0085 const: phy
0086
0087 hvcc-supply:
0088 description:
0089 The VCC power supply of the controller
0090
0091 ports:
0092 $ref: /schemas/graph.yaml#/properties/ports
0093
0094 properties:
0095 port@0:
0096 $ref: /schemas/graph.yaml#/properties/port
0097 description: |
0098 Input endpoints of the controller. Usually the associated
0099 TCON.
0100
0101 port@1:
0102 $ref: /schemas/graph.yaml#/properties/port
0103 description: |
0104 Output endpoints of the controller. Usually an HDMI
0105 connector.
0106
0107 required:
0108 - port@0
0109 - port@1
0110
0111 required:
0112 - compatible
0113 - reg
0114 - reg-io-width
0115 - interrupts
0116 - clocks
0117 - clock-names
0118 - resets
0119 - reset-names
0120 - phys
0121 - phy-names
0122 - ports
0123
0124 if:
0125 properties:
0126 compatible:
0127 contains:
0128 enum:
0129 - allwinner,sun50i-h6-dw-hdmi
0130
0131 then:
0132 properties:
0133 clocks:
0134 minItems: 6
0135
0136 clock-names:
0137 minItems: 6
0138
0139 resets:
0140 minItems: 2
0141
0142 reset-names:
0143 minItems: 2
0144
0145
0146 additionalProperties: false
0147
0148 examples:
0149 - |
0150 #include <dt-bindings/interrupt-controller/arm-gic.h>
0151
0152 /*
0153 * This comes from the clock/sun8i-a83t-ccu.h and
0154 * reset/sun8i-a83t-ccu.h headers, but we can't include them since
0155 * it would trigger a bunch of warnings for redefinitions of
0156 * symbols with the other example.
0157 */
0158 #define CLK_BUS_HDMI 39
0159 #define CLK_HDMI 93
0160 #define CLK_HDMI_SLOW 94
0161 #define RST_BUS_HDMI1 26
0162
0163 hdmi@1ee0000 {
0164 compatible = "allwinner,sun8i-a83t-dw-hdmi";
0165 reg = <0x01ee0000 0x10000>;
0166 reg-io-width = <1>;
0167 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0168 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
0169 <&ccu CLK_HDMI>;
0170 clock-names = "iahb", "isfr", "tmds";
0171 resets = <&ccu RST_BUS_HDMI1>;
0172 reset-names = "ctrl";
0173 phys = <&hdmi_phy>;
0174 phy-names = "phy";
0175 pinctrl-names = "default";
0176 pinctrl-0 = <&hdmi_pins>;
0177
0178 ports {
0179 #address-cells = <1>;
0180 #size-cells = <0>;
0181
0182 port@0 {
0183 reg = <0>;
0184
0185 endpoint {
0186 remote-endpoint = <&tcon1_out_hdmi>;
0187 };
0188 };
0189
0190 port@1 {
0191 reg = <1>;
0192 };
0193 };
0194 };
0195
0196 /* Cleanup after ourselves */
0197 #undef CLK_BUS_HDMI
0198 #undef CLK_HDMI
0199 #undef CLK_HDMI_SLOW
0200
0201 - |
0202 #include <dt-bindings/interrupt-controller/arm-gic.h>
0203
0204 /*
0205 * This comes from the clock/sun50i-h6-ccu.h and
0206 * reset/sun50i-h6-ccu.h headers, but we can't include them since
0207 * it would trigger a bunch of warnings for redefinitions of
0208 * symbols with the other example.
0209 */
0210 #define CLK_BUS_HDMI 126
0211 #define CLK_BUS_HDCP 137
0212 #define CLK_HDMI 123
0213 #define CLK_HDMI_SLOW 124
0214 #define CLK_HDMI_CEC 125
0215 #define CLK_HDCP 136
0216 #define RST_BUS_HDMI_SUB 57
0217 #define RST_BUS_HDCP 62
0218
0219 hdmi@6000000 {
0220 compatible = "allwinner,sun50i-h6-dw-hdmi";
0221 reg = <0x06000000 0x10000>;
0222 reg-io-width = <1>;
0223 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0224 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
0225 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
0226 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
0227 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
0228 "hdcp-bus";
0229 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
0230 reset-names = "ctrl", "hdcp";
0231 phys = <&hdmi_phy>;
0232 phy-names = "phy";
0233 pinctrl-names = "default";
0234 pinctrl-0 = <&hdmi_pins>;
0235
0236 ports {
0237 #address-cells = <1>;
0238 #size-cells = <0>;
0239
0240 port@0 {
0241 reg = <0>;
0242
0243 endpoint {
0244 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
0245 };
0246 };
0247
0248 port@1 {
0249 reg = <1>;
0250 };
0251 };
0252 };
0253
0254 ...
