0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-drc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner A31 Dynamic Range Controller Device Tree Bindings
0008
0009 maintainers:
0010 - Chen-Yu Tsai <wens@csie.org>
0011 - Maxime Ripard <mripard@kernel.org>
0012
0013 description: |
0014 The DRC (Dynamic Range Controller) allows to dynamically adjust
0015 pixel brightness/contrast based on histogram measurements for LCD
0016 content adaptive backlight control.
0017
0018 properties:
0019 compatible:
0020 enum:
0021 - allwinner,sun6i-a31-drc
0022 - allwinner,sun6i-a31s-drc
0023 - allwinner,sun8i-a23-drc
0024 - allwinner,sun8i-a33-drc
0025 - allwinner,sun9i-a80-drc
0026
0027 reg:
0028 maxItems: 1
0029
0030 interrupts:
0031 maxItems: 1
0032
0033 clocks:
0034 items:
0035 - description: The DRC interface clock
0036 - description: The DRC module clock
0037 - description: The DRC DRAM clock
0038
0039 clock-names:
0040 items:
0041 - const: ahb
0042 - const: mod
0043 - const: ram
0044
0045 resets:
0046 maxItems: 1
0047
0048 ports:
0049 $ref: /schemas/graph.yaml#/properties/ports
0050
0051 properties:
0052 port@0:
0053 $ref: /schemas/graph.yaml#/properties/port
0054 description: |
0055 Input endpoints of the controller.
0056
0057 port@1:
0058 $ref: /schemas/graph.yaml#/properties/port
0059 description: |
0060 Output endpoints of the controller.
0061
0062 required:
0063 - port@0
0064 - port@1
0065
0066 required:
0067 - compatible
0068 - reg
0069 - interrupts
0070 - clocks
0071 - clock-names
0072 - resets
0073 - ports
0074
0075 additionalProperties: false
0076
0077 examples:
0078 - |
0079 #include <dt-bindings/interrupt-controller/arm-gic.h>
0080
0081 #include <dt-bindings/clock/sun6i-a31-ccu.h>
0082 #include <dt-bindings/reset/sun6i-a31-ccu.h>
0083
0084 drc0: drc@1e70000 {
0085 compatible = "allwinner,sun6i-a31-drc";
0086 reg = <0x01e70000 0x10000>;
0087 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0088 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
0089 <&ccu CLK_DRAM_DRC0>;
0090 clock-names = "ahb", "mod",
0091 "ram";
0092 resets = <&ccu RST_AHB1_DRC0>;
0093
0094 ports {
0095 #address-cells = <1>;
0096 #size-cells = <0>;
0097
0098 drc0_in: port@0 {
0099 reg = <0>;
0100
0101 drc0_in_be0: endpoint {
0102 remote-endpoint = <&be0_out_drc0>;
0103 };
0104 };
0105
0106 drc0_out: port@1 {
0107 #address-cells = <1>;
0108 #size-cells = <0>;
0109 reg = <1>;
0110
0111 drc0_out_tcon0: endpoint@0 {
0112 reg = <0>;
0113 remote-endpoint = <&tcon0_in_drc0>;
0114 };
0115
0116 drc0_out_tcon1: endpoint@1 {
0117 reg = <1>;
0118 remote-endpoint = <&tcon1_in_drc0>;
0119 };
0120 };
0121 };
0122 };
0123
0124
0125 ...
