bindings/devfreq/nvidia%2Ctegra30-actmon.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra30 Activity Monitor
0008
0009 maintainers:
0010   - Dmitry Osipenko <digetx@gmail.com>
0011   - Jon Hunter <jonathanh@nvidia.com>
0012   - Thierry Reding <thierry.reding@gmail.com>
0013
0014 description: |
0015   The activity monitor block collects statistics about the behaviour of other
0016   components in the system. This information can be used to derive the rate at
0017   which the external memory needs to be clocked in order to serve all requests
0018   from the monitored clients.
0019
0020 properties:
0021   compatible:
0022     enum:
0023       - nvidia,tegra30-actmon
0024       - nvidia,tegra114-actmon
0025       - nvidia,tegra124-actmon
0026       - nvidia,tegra210-actmon
0027
0028   reg:
0029     maxItems: 1
0030
0031   clocks:
0032     maxItems: 2
0033
0034   clock-names:
0035     items:
0036       - const: actmon
0037       - const: emc
0038
0039   resets:
0040     maxItems: 1
0041
0042   reset-names:
0043     items:
0044       - const: actmon
0045
0046   interrupts:
0047     maxItems: 1
0048
0049   interconnects:
0050     minItems: 1
0051     maxItems: 12
0052
0053   interconnect-names:
0054     minItems: 1
0055     maxItems: 12
0056     description:
0057       Should include name of the interconnect path for each interconnect
0058       entry. Consult TRM documentation for information about available
0059       memory clients, see MEMORY CONTROLLER and ACTIVITY MONITOR sections.
0060
0061   operating-points-v2:
0062     description:
0063       Should contain freqs and voltages and opp-supported-hw property, which
0064       is a bitfield indicating SoC speedo ID mask.
0065
0066   "#cooling-cells":
0067     const: 2
0068
0069 required:
0070   - compatible
0071   - reg
0072   - clocks
0073   - clock-names
0074   - resets
0075   - reset-names
0076   - interrupts
0077   - interconnects
0078   - interconnect-names
0079   - operating-points-v2
0080   - "#cooling-cells"
0081
0082 additionalProperties: false
0083
0084 examples:
0085   - |
0086     #include <dt-bindings/memory/tegra30-mc.h>
0087
0088     mc: memory-controller@7000f000 {
0089         compatible = "nvidia,tegra30-mc";
0090         reg = <0x7000f000 0x400>;
0091         clocks = <&clk 32>;
0092         clock-names = "mc";
0093
0094         interrupts = <0 77 4>;
0095
0096         #iommu-cells = <1>;
0097         #reset-cells = <1>;
0098         #interconnect-cells = <1>;
0099     };
0100
0101     emc: external-memory-controller@7000f400 {
0102         compatible = "nvidia,tegra30-emc";
0103         reg = <0x7000f400 0x400>;
0104         interrupts = <0 78 4>;
0105         clocks = <&clk 57>;
0106
0107         nvidia,memory-controller = <&mc>;
0108         operating-points-v2 = <&dvfs_opp_table>;
0109         power-domains = <&domain>;
0110
0111         #interconnect-cells = <0>;
0112     };
0113
0114     actmon@6000c800 {
0115         compatible = "nvidia,tegra30-actmon";
0116         reg = <0x6000c800 0x400>;
0117         interrupts = <0 45 4>;
0118         clocks = <&clk 119>, <&clk 57>;
0119         clock-names = "actmon", "emc";
0120         resets = <&rst 119>;
0121         reset-names = "actmon";
0122         operating-points-v2 = <&dvfs_opp_table>;
0123         interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
0124         interconnect-names = "cpu-read";
0125         #cooling-cells = <2>;
0126     };