bindings/crypto/intel%2Ckeembay-ocs-aes.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-aes.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Intel Keem Bay OCS AES Device Tree Bindings
0008
0009 maintainers:
0010   - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
0011
0012 description:
0013   The Intel Keem Bay Offload and Crypto Subsystem (OCS) AES engine provides
0014   hardware-accelerated AES/SM4 encryption/decryption.
0015
0016 properties:
0017   compatible:
0018     const: intel,keembay-ocs-aes
0019
0020   reg:
0021     maxItems: 1
0022
0023   interrupts:
0024     maxItems: 1
0025
0026   clocks:
0027     maxItems: 1
0028
0029 required:
0030   - compatible
0031   - reg
0032   - interrupts
0033   - clocks
0034
0035 additionalProperties: false
0036
0037 examples:
0038   - |
0039     #include <dt-bindings/interrupt-controller/arm-gic.h>
0040     crypto@30008000 {
0041       compatible = "intel,keembay-ocs-aes";
0042       reg = <0x30008000 0x1000>;
0043       interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0044       clocks = <&scmi_clk 95>;
0045     };