0001 Inside Secure SafeXcel cryptographic engine
0002
0003 Required properties:
0004 - compatible: Should be "inside-secure,safexcel-eip197b",
0005 "inside-secure,safexcel-eip197d" or
0006 "inside-secure,safexcel-eip97ies".
0007 - reg: Base physical address of the engine and length of memory mapped region.
0008 - interrupts: Interrupt numbers for the rings and engine.
0009 - interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
0010
0011 Optional properties:
0012 - clocks: Reference to the crypto engine clocks, the second clock is
0013 needed for the Armada 7K/8K SoCs.
0014 - clock-names: mandatory if there is a second clock, in this case the
0015 name must be "core" for the first clock and "reg" for
0016 the second one.
0017
0018 Backward compatibility:
0019 Two compatibles are kept for backward compatibility, but shouldn't be used for
0020 new submissions:
0021 - "inside-secure,safexcel-eip197" is equivalent to
0022 "inside-secure,safexcel-eip197b".
0023 - "inside-secure,safexcel-eip97" is equivalent to
0024 "inside-secure,safexcel-eip97ies".
0025
0026 Example:
0027
0028 crypto: crypto@800000 {
0029 compatible = "inside-secure,safexcel-eip197b";
0030 reg = <0x800000 0x200000>;
0031 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0032 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0033 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0034 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
0035 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0036 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0037 interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
0038 "eip";
0039 clocks = <&cpm_syscon0 1 26>;
0040 };
