0001 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
0002 Currently Freescale powerpc chip C29X is embedded with SEC 6.
0003 SEC 6 device tree binding include:
0004 -SEC 6 Node
0005 -Job Ring Node
0006 -Full Example
0007
0008 =====================================================================
0009 SEC 6 Node
0010
0011 Description
0012
0013 Node defines the base address of the SEC 6 block.
0014 This block specifies the address range of all global
0015 configuration registers for the SEC 6 block.
0016 For example, In C293, we could see three SEC 6 node.
0017
0018 PROPERTIES
0019
0020 - compatible
0021 Usage: required
0022 Value type: <string>
0023 Definition: Must include "fsl,sec-v6.0".
0024
0025 - fsl,sec-era
0026 Usage: optional
0027 Value type: <u32>
0028 Definition: A standard property. Define the 'ERA' of the SEC
0029 device.
0030
0031 - #address-cells
0032 Usage: required
0033 Value type: <u32>
0034 Definition: A standard property. Defines the number of cells
0035 for representing physical addresses in child nodes.
0036
0037 - #size-cells
0038 Usage: required
0039 Value type: <u32>
0040 Definition: A standard property. Defines the number of cells
0041 for representing the size of physical addresses in
0042 child nodes.
0043
0044 - reg
0045 Usage: required
0046 Value type: <prop-encoded-array>
0047 Definition: A standard property. Specifies the physical
0048 address and length of the SEC 6 configuration registers.
0049
0050 - ranges
0051 Usage: required
0052 Value type: <prop-encoded-array>
0053 Definition: A standard property. Specifies the physical address
0054 range of the SEC 6.0 register space (-SNVS not included). A
0055 triplet that includes the child address, parent address, &
0056 length.
0057
0058 Note: All other standard properties (see the Devicetree Specification)
0059 are allowed but are optional.
0060
0061 EXAMPLE
0062 crypto@a0000 {
0063 compatible = "fsl,sec-v6.0";
0064 fsl,sec-era = <6>;
0065 #address-cells = <1>;
0066 #size-cells = <1>;
0067 reg = <0xa0000 0x20000>;
0068 ranges = <0 0xa0000 0x20000>;
0069 };
0070
0071 =====================================================================
0072 Job Ring (JR) Node
0073
0074 Child of the crypto node defines data processing interface to SEC 6
0075 across the peripheral bus for purposes of processing
0076 cryptographic descriptors. The specified address
0077 range can be made visible to one (or more) cores.
0078 The interrupt defined for this node is controlled within
0079 the address range of this node.
0080
0081 - compatible
0082 Usage: required
0083 Value type: <string>
0084 Definition: Must include "fsl,sec-v6.0-job-ring".
0085
0086 - reg
0087 Usage: required
0088 Value type: <prop-encoded-array>
0089 Definition: Specifies a two JR parameters: an offset from
0090 the parent physical address and the length the JR registers.
0091
0092 - interrupts
0093 Usage: required
0094 Value type: <prop_encoded-array>
0095 Definition: Specifies the interrupts generated by this
0096 device. The value of the interrupts property
0097 consists of one interrupt specifier. The format
0098 of the specifier is defined by the binding document
0099 describing the node's interrupt parent.
0100
0101 EXAMPLE
0102 jr@1000 {
0103 compatible = "fsl,sec-v6.0-job-ring";
0104 reg = <0x1000 0x1000>;
0105 interrupts = <49 2 0 0>;
0106 };
0107
0108 ===================================================================
0109 Full Example
0110
0111 Since some chips may contain more than one SEC, the dtsi contains
0112 only the node contents, not the node itself. A chip using the SEC
0113 should include the dtsi inside each SEC node. Example:
0114
0115 In qoriq-sec6.0.dtsi:
0116
0117 compatible = "fsl,sec-v6.0";
0118 fsl,sec-era = <6>;
0119 #address-cells = <1>;
0120 #size-cells = <1>;
0121
0122 jr@1000 {
0123 compatible = "fsl,sec-v6.0-job-ring",
0124 "fsl,sec-v5.2-job-ring",
0125 "fsl,sec-v5.0-job-ring",
0126 "fsl,sec-v4.4-job-ring",
0127 "fsl,sec-v4.0-job-ring";
0128 reg = <0x1000 0x1000>;
0129 };
0130
0131 jr@2000 {
0132 compatible = "fsl,sec-v6.0-job-ring",
0133 "fsl,sec-v5.2-job-ring",
0134 "fsl,sec-v5.0-job-ring",
0135 "fsl,sec-v4.4-job-ring",
0136 "fsl,sec-v4.0-job-ring";
0137 reg = <0x2000 0x1000>;
0138 };
0139
0140 In the C293 device tree, we add the include of public property:
0141
0142 crypto@a0000 {
0143 /include/ "qoriq-sec6.0.dtsi"
0144 }
0145
0146 crypto@a0000 {
0147 reg = <0xa0000 0x20000>;
0148 ranges = <0 0xa0000 0x20000>;
0149
0150 jr@1000 {
0151 interrupts = <49 2 0 0>;
0152 };
0153
0154 jr@2000 {
0155 interrupts = <50 2 0 0>;
0156 };
0157 };
