0001 =====================================================================
0002 SEC 4 Device Tree Binding
0003 Copyright (C) 2008-2011 Freescale Semiconductor Inc.
0004
0005 CONTENTS
0006 -Overview
0007 -SEC 4 Node
0008 -Job Ring Node
0009 -Run Time Integrity Check (RTIC) Node
0010 -Run Time Integrity Check (RTIC) Memory Node
0011 -Secure Non-Volatile Storage (SNVS) Node
0012 -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
0013 -Full Example
0014
0015 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
0016 Accelerator and Assurance Module (CAAM).
0017
0018 =====================================================================
0019 Overview
0020
0021 DESCRIPTION
0022
0023 SEC 4 h/w can process requests from 2 types of sources.
0024 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
0025 2. Job Rings (HW interface between cores & SEC 4 registers).
0026
0027 High Speed Data Path Configuration:
0028
0029 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
0030 such as the P4080. The number of simultaneous dequeues the QI can make is
0031 equal to the number of Descriptor Controller (DECO) engines in a particular
0032 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
0033 dequeue from 5 subportals simultaneously.
0034
0035 Job Ring Data Path Configuration:
0036
0037 Each JR is located on a separate 4k page, they may (or may not) be made visible
0038 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
0039 up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
0040
0041 =====================================================================
0042 SEC 4 Node
0043
0044 Description
0045
0046 Node defines the base address of the SEC 4 block.
0047 This block specifies the address range of all global
0048 configuration registers for the SEC 4 block. It
0049 also receives interrupts from the Run Time Integrity Check
0050 (RTIC) function within the SEC 4 block.
0051
0052 PROPERTIES
0053
0054 - compatible
0055 Usage: required
0056 Value type: <string>
0057 Definition: Must include "fsl,sec-v4.0"
0058
0059 - fsl,sec-era
0060 Usage: optional
0061 Value type: <u32>
0062 Definition: A standard property. Define the 'ERA' of the SEC
0063 device.
0064
0065 - #address-cells
0066 Usage: required
0067 Value type: <u32>
0068 Definition: A standard property. Defines the number of cells
0069 for representing physical addresses in child nodes.
0070
0071 - #size-cells
0072 Usage: required
0073 Value type: <u32>
0074 Definition: A standard property. Defines the number of cells
0075 for representing the size of physical addresses in
0076 child nodes.
0077
0078 - reg
0079 Usage: required
0080 Value type: <prop-encoded-array>
0081 Definition: A standard property. Specifies the physical
0082 address and length of the SEC4 configuration registers.
0083 registers
0084
0085 - ranges
0086 Usage: required
0087 Value type: <prop-encoded-array>
0088 Definition: A standard property. Specifies the physical address
0089 range of the SEC 4.0 register space (-SNVS not included). A
0090 triplet that includes the child address, parent address, &
0091 length.
0092
0093 - interrupts
0094 Usage: required
0095 Value type: <prop_encoded-array>
0096 Definition: Specifies the interrupts generated by this
0097 device. The value of the interrupts property
0098 consists of one interrupt specifier. The format
0099 of the specifier is defined by the binding document
0100 describing the node's interrupt parent.
0101
0102 - clocks
0103 Usage: required if SEC 4.0 requires explicit enablement of clocks
0104 Value type: <prop_encoded-array>
0105 Definition: A list of phandle and clock specifier pairs describing
0106 the clocks required for enabling and disabling SEC 4.0.
0107
0108 - clock-names
0109 Usage: required if SEC 4.0 requires explicit enablement of clocks
0110 Value type: <string>
0111 Definition: A list of clock name strings in the same order as the
0112 clocks property.
0113
0114 Note: All other standard properties (see the Devicetree Specification)
0115 are allowed but are optional.
0116
0117
0118 EXAMPLE
0119
0120 iMX6QDL/SX requires four clocks
0121
0122 crypto@300000 {
0123 compatible = "fsl,sec-v4.0";
0124 fsl,sec-era = <2>;
0125 #address-cells = <1>;
0126 #size-cells = <1>;
0127 reg = <0x300000 0x10000>;
0128 ranges = <0 0x300000 0x10000>;
0129 interrupt-parent = <&mpic>;
0130 interrupts = <92 2>;
0131 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
0132 <&clks IMX6QDL_CLK_CAAM_ACLK>,
0133 <&clks IMX6QDL_CLK_CAAM_IPG>,
0134 <&clks IMX6QDL_CLK_EIM_SLOW>;
0135 clock-names = "mem", "aclk", "ipg", "emi_slow";
0136 };
0137
0138
0139 iMX6UL does only require three clocks
0140
0141 crypto: crypto@2140000 {
0142 compatible = "fsl,sec-v4.0";
0143 #address-cells = <1>;
0144 #size-cells = <1>;
0145 reg = <0x2140000 0x3c000>;
0146 ranges = <0 0x2140000 0x3c000>;
0147 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0148
0149 clocks = <&clks IMX6UL_CLK_CAAM_MEM>,
0150 <&clks IMX6UL_CLK_CAAM_ACLK>,
0151 <&clks IMX6UL_CLK_CAAM_IPG>;
0152 clock-names = "mem", "aclk", "ipg";
0153 };
0154
0155 =====================================================================
0156 Job Ring (JR) Node
0157
0158 Child of the crypto node defines data processing interface to SEC 4
0159 across the peripheral bus for purposes of processing
0160 cryptographic descriptors. The specified address
0161 range can be made visible to one (or more) cores.
0162 The interrupt defined for this node is controlled within
0163 the address range of this node.
0164
0165 - compatible
0166 Usage: required
0167 Value type: <string>
0168 Definition: Must include "fsl,sec-v4.0-job-ring"
0169
0170 - reg
0171 Usage: required
0172 Value type: <prop-encoded-array>
0173 Definition: Specifies a two JR parameters: an offset from
0174 the parent physical address and the length the JR registers.
0175
0176 - fsl,liodn
0177 Usage: optional-but-recommended
0178 Value type: <prop-encoded-array>
0179 Definition:
0180 Specifies the LIODN to be used in conjunction with
0181 the ppid-to-liodn table that specifies the PPID to LIODN mapping.
0182 Needed if the PAMU is used. Value is a 12 bit value
0183 where value is a LIODN ID for this JR. This property is
0184 normally set by boot firmware.
0185
0186 - interrupts
0187 Usage: required
0188 Value type: <prop_encoded-array>
0189 Definition: Specifies the interrupts generated by this
0190 device. The value of the interrupts property
0191 consists of one interrupt specifier. The format
0192 of the specifier is defined by the binding document
0193 describing the node's interrupt parent.
0194
0195 EXAMPLE
0196 jr@1000 {
0197 compatible = "fsl,sec-v4.0-job-ring";
0198 reg = <0x1000 0x1000>;
0199 fsl,liodn = <0x081>;
0200 interrupt-parent = <&mpic>;
0201 interrupts = <88 2>;
0202 };
0203
0204
0205 =====================================================================
0206 Run Time Integrity Check (RTIC) Node
0207
0208 Child node of the crypto node. Defines a register space that
0209 contains up to 5 sets of addresses and their lengths (sizes) that
0210 will be checked at run time. After an initial hash result is
0211 calculated, these addresses are checked by HW to monitor any
0212 change. If any memory is modified, a Security Violation is
0213 triggered (see SNVS definition).
0214
0215
0216 - compatible
0217 Usage: required
0218 Value type: <string>
0219 Definition: Must include "fsl,sec-v4.0-rtic".
0220
0221 - #address-cells
0222 Usage: required
0223 Value type: <u32>
0224 Definition: A standard property. Defines the number of cells
0225 for representing physical addresses in child nodes. Must
0226 have a value of 1.
0227
0228 - #size-cells
0229 Usage: required
0230 Value type: <u32>
0231 Definition: A standard property. Defines the number of cells
0232 for representing the size of physical addresses in
0233 child nodes. Must have a value of 1.
0234
0235 - reg
0236 Usage: required
0237 Value type: <prop-encoded-array>
0238 Definition: A standard property. Specifies a two parameters:
0239 an offset from the parent physical address and the length
0240 the SEC4 registers.
0241
0242 - ranges
0243 Usage: required
0244 Value type: <prop-encoded-array>
0245 Definition: A standard property. Specifies the physical address
0246 range of the SEC 4 register space (-SNVS not included). A
0247 triplet that includes the child address, parent address, &
0248 length.
0249
0250 EXAMPLE
0251 rtic@6000 {
0252 compatible = "fsl,sec-v4.0-rtic";
0253 #address-cells = <1>;
0254 #size-cells = <1>;
0255 reg = <0x6000 0x100>;
0256 ranges = <0x0 0x6100 0xe00>;
0257 };
0258
0259 =====================================================================
0260 Run Time Integrity Check (RTIC) Memory Node
0261 A child node that defines individual RTIC memory regions that are used to
0262 perform run-time integrity check of memory areas that should not modified.
0263 The node defines a register that contains the memory address &
0264 length (combined) and a second register that contains the hash result
0265 in big endian format.
0266
0267 - compatible
0268 Usage: required
0269 Value type: <string>
0270 Definition: Must include "fsl,sec-v4.0-rtic-memory".
0271
0272 - reg
0273 Usage: required
0274 Value type: <prop-encoded-array>
0275 Definition: A standard property. Specifies two parameters:
0276 an offset from the parent physical address and the length:
0277
0278 1. The location of the RTIC memory address & length registers.
0279 2. The location RTIC hash result.
0280
0281 - fsl,rtic-region
0282 Usage: optional-but-recommended
0283 Value type: <prop-encoded-array>
0284 Definition:
0285 Specifies the HW address (36 bit address) for this region
0286 followed by the length of the HW partition to be checked;
0287 the address is represented as a 64 bit quantity followed
0288 by a 32 bit length.
0289
0290 - fsl,liodn
0291 Usage: optional-but-recommended
0292 Value type: <prop-encoded-array>
0293 Definition:
0294 Specifies the LIODN to be used in conjunction with
0295 the ppid-to-liodn table that specifies the PPID to LIODN
0296 mapping. Needed if the PAMU is used. Value is a 12 bit value
0297 where value is a LIODN ID for this RTIC memory region. This
0298 property is normally set by boot firmware.
0299
0300 EXAMPLE
0301 rtic-a@0 {
0302 compatible = "fsl,sec-v4.0-rtic-memory";
0303 reg = <0x00 0x20 0x100 0x80>;
0304 fsl,liodn = <0x03c>;
0305 fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
0306 };
0307
0308 =====================================================================
0309 Secure Non-Volatile Storage (SNVS) Node
0310
0311 Node defines address range and the associated
0312 interrupt for the SNVS function. This function
0313 monitors security state information & reports
0314 security violations. This also included rtc,
0315 system power off and ON/OFF key.
0316
0317 - compatible
0318 Usage: required
0319 Value type: <string>
0320 Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
0321
0322 - reg
0323 Usage: required
0324 Value type: <prop-encoded-array>
0325 Definition: A standard property. Specifies the physical
0326 address and length of the SEC4 configuration
0327 registers.
0328
0329 - #address-cells
0330 Usage: required
0331 Value type: <u32>
0332 Definition: A standard property. Defines the number of cells
0333 for representing physical addresses in child nodes. Must
0334 have a value of 1.
0335
0336 - #size-cells
0337 Usage: required
0338 Value type: <u32>
0339 Definition: A standard property. Defines the number of cells
0340 for representing the size of physical addresses in
0341 child nodes. Must have a value of 1.
0342
0343 - ranges
0344 Usage: required
0345 Value type: <prop-encoded-array>
0346 Definition: A standard property. Specifies the physical address
0347 range of the SNVS register space. A triplet that includes
0348 the child address, parent address, & length.
0349
0350 - interrupts
0351 Usage: optional
0352 Value type: <prop_encoded-array>
0353 Definition: Specifies the interrupts generated by this
0354 device. The value of the interrupts property
0355 consists of one interrupt specifier. The format
0356 of the specifier is defined by the binding document
0357 describing the node's interrupt parent.
0358
0359 EXAMPLE
0360 sec_mon@314000 {
0361 compatible = "fsl,sec-v4.0-mon", "syscon";
0362 reg = <0x314000 0x1000>;
0363 ranges = <0 0x314000 0x1000>;
0364 interrupt-parent = <&mpic>;
0365 interrupts = <93 2>;
0366 };
0367
0368 =====================================================================
0369 Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
0370
0371 A SNVS child node that defines SNVS LP RTC.
0372
0373 - compatible
0374 Usage: required
0375 Value type: <string>
0376 Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
0377
0378 - interrupts
0379 Usage: required
0380 Value type: <prop_encoded-array>
0381 Definition: Specifies the interrupts generated by this
0382 device. The value of the interrupts property
0383 consists of one interrupt specifier. The format
0384 of the specifier is defined by the binding document
0385 describing the node's interrupt parent.
0386
0387 - regmap
0388 Usage: required
0389 Value type: <phandle>
0390 Definition: this is phandle to the register map node.
0391
0392 - offset
0393 Usage: option
0394 value type: <u32>
0395 Definition: LP register offset. default it is 0x34.
0396
0397 - clocks
0398 Usage: optional, required if SNVS LP RTC requires explicit
0399 enablement of clocks
0400 Value type: <prop_encoded-array>
0401 Definition: a clock specifier describing the clock required for
0402 enabling and disabling SNVS LP RTC.
0403
0404 - clock-names
0405 Usage: optional, required if SNVS LP RTC requires explicit
0406 enablement of clocks
0407 Value type: <string>
0408 Definition: clock name string should be "snvs-rtc".
0409
0410 EXAMPLE
0411 sec_mon_rtc_lp@1 {
0412 compatible = "fsl,sec-v4.0-mon-rtc-lp";
0413 interrupts = <93 2>;
0414 regmap = <&snvs>;
0415 offset = <0x34>;
0416 clocks = <&clks IMX7D_SNVS_CLK>;
0417 clock-names = "snvs-rtc";
0418 };
0419
0420 =====================================================================
0421 System ON/OFF key driver
0422
0423 The snvs-pwrkey is designed to enable POWER key function which controlled
0424 by SNVS ONOFF, the driver can report the status of POWER key and wakeup
0425 system if pressed after system suspend.
0426
0427 - compatible:
0428 Usage: required
0429 Value type: <string>
0430 Definition: Mush include "fsl,sec-v4.0-pwrkey".
0431
0432 - interrupts:
0433 Usage: required
0434 Value type: <prop_encoded-array>
0435 Definition: The SNVS ON/OFF interrupt number to the CPU(s).
0436
0437 - linux,keycode:
0438 Usage: option
0439 Value type: <int>
0440 Definition: Keycode to emit, KEY_POWER by default.
0441
0442 - wakeup-source:
0443 Usage: option
0444 Value type: <boo>
0445 Definition: Button can wake-up the system.
0446
0447 - regmap:
0448 Usage: required:
0449 Value type: <phandle>
0450 Definition: this is phandle to the register map node.
0451
0452 EXAMPLE:
0453 snvs-pwrkey@020cc000 {
0454 compatible = "fsl,sec-v4.0-pwrkey";
0455 regmap = <&snvs>;
0456 interrupts = <0 4 0x4>
0457 linux,keycode = <116>; /* KEY_POWER */
0458 wakeup-source;
0459 };
0460
0461 =====================================================================
0462 FULL EXAMPLE
0463
0464 crypto: crypto@300000 {
0465 compatible = "fsl,sec-v4.0";
0466 #address-cells = <1>;
0467 #size-cells = <1>;
0468 reg = <0x300000 0x10000>;
0469 ranges = <0 0x300000 0x10000>;
0470 interrupt-parent = <&mpic>;
0471 interrupts = <92 2>;
0472
0473 sec_jr0: jr@1000 {
0474 compatible = "fsl,sec-v4.0-job-ring";
0475 reg = <0x1000 0x1000>;
0476 interrupt-parent = <&mpic>;
0477 interrupts = <88 2>;
0478 };
0479
0480 sec_jr1: jr@2000 {
0481 compatible = "fsl,sec-v4.0-job-ring";
0482 reg = <0x2000 0x1000>;
0483 interrupt-parent = <&mpic>;
0484 interrupts = <89 2>;
0485 };
0486
0487 sec_jr2: jr@3000 {
0488 compatible = "fsl,sec-v4.0-job-ring";
0489 reg = <0x3000 0x1000>;
0490 interrupt-parent = <&mpic>;
0491 interrupts = <90 2>;
0492 };
0493
0494 sec_jr3: jr@4000 {
0495 compatible = "fsl,sec-v4.0-job-ring";
0496 reg = <0x4000 0x1000>;
0497 interrupt-parent = <&mpic>;
0498 interrupts = <91 2>;
0499 };
0500
0501 rtic@6000 {
0502 compatible = "fsl,sec-v4.0-rtic";
0503 #address-cells = <1>;
0504 #size-cells = <1>;
0505 reg = <0x6000 0x100>;
0506 ranges = <0x0 0x6100 0xe00>;
0507
0508 rtic_a: rtic-a@0 {
0509 compatible = "fsl,sec-v4.0-rtic-memory";
0510 reg = <0x00 0x20 0x100 0x80>;
0511 };
0512
0513 rtic_b: rtic-b@20 {
0514 compatible = "fsl,sec-v4.0-rtic-memory";
0515 reg = <0x20 0x20 0x200 0x80>;
0516 };
0517
0518 rtic_c: rtic-c@40 {
0519 compatible = "fsl,sec-v4.0-rtic-memory";
0520 reg = <0x40 0x20 0x300 0x80>;
0521 };
0522
0523 rtic_d: rtic-d@60 {
0524 compatible = "fsl,sec-v4.0-rtic-memory";
0525 reg = <0x60 0x20 0x500 0x80>;
0526 };
0527 };
0528 };
0529
0530 sec_mon: sec_mon@314000 {
0531 compatible = "fsl,sec-v4.0-mon";
0532 reg = <0x314000 0x1000>;
0533 ranges = <0 0x314000 0x1000>;
0534
0535 sec_mon_rtc_lp@34 {
0536 compatible = "fsl,sec-v4.0-mon-rtc-lp";
0537 regmap = <&sec_mon>;
0538 offset = <0x34>;
0539 interrupts = <93 2>;
0540 clocks = <&clks IMX7D_SNVS_CLK>;
0541 clock-names = "snvs-rtc";
0542 };
0543
0544 snvs-pwrkey@020cc000 {
0545 compatible = "fsl,sec-v4.0-pwrkey";
0546 regmap = <&sec_mon>;
0547 interrupts = <0 4 0x4>;
0548 linux,keycode = <116>; /* KEY_POWER */
0549 wakeup-source;
0550 };
0551 };
0552
0553 =====================================================================
