0001 Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
0002
0003 Required properties:
0004
0005 - compatible : Should contain entries for this and backward compatible
0006 SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3)
0007 e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1)
0008 warning: SEC1 and SEC2 are mutually exclusive
0009 - reg : Offset and length of the register set for the device
0010 - interrupts : the SEC's interrupt number
0011 - fsl,num-channels : An integer representing the number of channels
0012 available.
0013 - fsl,channel-fifo-len : An integer representing the number of
0014 descriptor pointers each channel fetch fifo can hold.
0015 - fsl,exec-units-mask : The bitmask representing what execution units
0016 (EUs) are available. It's a single 32-bit cell. EU information
0017 should be encoded following the SEC's Descriptor Header Dword
0018 EU_SEL0 field documentation, i.e. as follows:
0019
0020 bit 0 = reserved - should be 0
0021 bit 1 = set if SEC has the ARC4 EU (AFEU)
0022 bit 2 = set if SEC has the DES/3DES EU (DEU)
0023 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
0024 bit 4 = set if SEC has the random number generator EU (RNG)
0025 bit 5 = set if SEC has the public key EU (PKEU)
0026 bit 6 = set if SEC has the AES EU (AESU)
0027 bit 7 = set if SEC has the Kasumi EU (KEU)
0028 bit 8 = set if SEC has the CRC EU (CRCU)
0029 bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
0030
0031 remaining bits are reserved for future SEC EUs.
0032
0033 - fsl,descriptor-types-mask : The bitmask representing what descriptors
0034 are available. It's a single 32-bit cell. Descriptor type information
0035 should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
0036 field documentation, i.e. as follows:
0037
0038 bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
0039 bit 1 = set if SEC supports the ipsec_esp descriptor type
0040 bit 2 = set if SEC supports the common_nonsnoop desc. type
0041 bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
0042 bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
0043 bit 5 = set if SEC supports the srtp descriptor type
0044 bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
0045 bit 7 = set if SEC supports the pkeu_assemble descriptor type
0046 bit 8 = set if SEC supports the aesu_key_expand_output desc.type
0047 bit 9 = set if SEC supports the pkeu_ptmul descriptor type
0048 bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
0049 bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
0050
0051 ..and so on and so forth.
0052
0053 Example:
0054
0055 /* MPC8548E */
0056 crypto@30000 {
0057 compatible = "fsl,sec2.1", "fsl,sec2.0";
0058 reg = <0x30000 0x10000>;
0059 interrupts = <29 2>;
0060 interrupt-parent = <&mpic>;
0061 fsl,num-channels = <4>;
0062 fsl,channel-fifo-len = <24>;
0063 fsl,exec-units-mask = <0xfe>;
0064 fsl,descriptor-types-mask = <0x12b0ebf>;
0065 };
