0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-sha.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator
0009
0010 maintainers:
0011 - Tudor Ambarus <tudor.ambarus@microchip.com>
0012
0013 properties:
0014 compatible:
0015 const: atmel,at91sam9g46-sha
0016
0017 reg:
0018 maxItems: 1
0019
0020 interrupts:
0021 maxItems: 1
0022
0023 clocks:
0024 maxItems: 1
0025
0026 clock-names:
0027 const: sha_clk
0028
0029 dmas:
0030 maxItems: 1
0031 description: TX DMA Channel
0032
0033 dma-names:
0034 const: tx
0035
0036 required:
0037 - compatible
0038 - reg
0039 - interrupts
0040 - clocks
0041 - clock-names
0042
0043 additionalProperties: false
0044
0045 examples:
0046 - |
0047 #include <dt-bindings/interrupt-controller/irq.h>
0048 #include <dt-bindings/interrupt-controller/arm-gic.h>
0049 #include <dt-bindings/clock/at91.h>
0050 #include <dt-bindings/dma/at91.h>
0051
0052 sha: crypto@e1814000 {
0053 compatible = "atmel,at91sam9g46-sha";
0054 reg = <0xe1814000 0x100>;
0055 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0056 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
0057 clock-names = "sha_clk";
0058 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
0059 dma-names = "tx";
0060 };
