0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Technologies, Inc. NVMEM CPUFreq bindings
0008
0009 maintainers:
0010 - Ilia Lin <ilia.lin@kernel.org>
0011
0012 description: |
0013 In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply
0014 voltage is dynamically configured by Core Power Reduction (CPR) depending on
0015 current CPU frequency and efuse values.
0016 CPR provides a power domain with multiple levels that are selected depending
0017 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
0018 according to the required OPPs defined in the CPU OPP tables.
0019
0020 select:
0021 properties:
0022 compatible:
0023 contains:
0024 enum:
0025 - qcom,apq8064
0026 - qcom,apq8096
0027 - qcom,ipq8064
0028 - qcom,msm8939
0029 - qcom,msm8960
0030 - qcom,msm8974
0031 - qcom,msm8996
0032 - qcom,qcs404
0033 required:
0034 - compatible
0035
0036 properties:
0037 cpus:
0038 type: object
0039
0040 patternProperties:
0041 'cpu@[0-9a-f]+':
0042 type: object
0043
0044 properties:
0045 power-domains:
0046 maxItems: 1
0047
0048 power-domain-names:
0049 items:
0050 - const: cpr
0051
0052 required:
0053 - power-domains
0054 - power-domain-names
0055
0056 patternProperties:
0057 '^opp-table(-[a-z0-9]+)?$':
0058 if:
0059 properties:
0060 compatible:
0061 const: operating-points-v2-kryo-cpu
0062 then:
0063 patternProperties:
0064 '^opp-?[0-9]+$':
0065 required:
0066 - required-opps
0067
0068 additionalProperties: true
0069
0070 examples:
0071 - |
0072 / {
0073 model = "Qualcomm Technologies, Inc. QCS404 EVB 1000";
0074 compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", "qcom,qcs404";
0075 #address-cells = <2>;
0076 #size-cells = <2>;
0077
0078 cpus {
0079 #address-cells = <1>;
0080 #size-cells = <0>;
0081
0082 CPU0: cpu@100 {
0083 device_type = "cpu";
0084 compatible = "arm,cortex-a53";
0085 reg = <0x100>;
0086 enable-method = "psci";
0087 cpu-idle-states = <&CPU_SLEEP_0>;
0088 next-level-cache = <&L2_0>;
0089 #cooling-cells = <2>;
0090 clocks = <&apcs_glb>;
0091 operating-points-v2 = <&cpu_opp_table>;
0092 power-domains = <&cpr>;
0093 power-domain-names = "cpr";
0094 };
0095
0096 CPU1: cpu@101 {
0097 device_type = "cpu";
0098 compatible = "arm,cortex-a53";
0099 reg = <0x101>;
0100 enable-method = "psci";
0101 cpu-idle-states = <&CPU_SLEEP_0>;
0102 next-level-cache = <&L2_0>;
0103 #cooling-cells = <2>;
0104 clocks = <&apcs_glb>;
0105 operating-points-v2 = <&cpu_opp_table>;
0106 power-domains = <&cpr>;
0107 power-domain-names = "cpr";
0108 };
0109
0110 CPU2: cpu@102 {
0111 device_type = "cpu";
0112 compatible = "arm,cortex-a53";
0113 reg = <0x102>;
0114 enable-method = "psci";
0115 cpu-idle-states = <&CPU_SLEEP_0>;
0116 next-level-cache = <&L2_0>;
0117 #cooling-cells = <2>;
0118 clocks = <&apcs_glb>;
0119 operating-points-v2 = <&cpu_opp_table>;
0120 power-domains = <&cpr>;
0121 power-domain-names = "cpr";
0122 };
0123
0124 CPU3: cpu@103 {
0125 device_type = "cpu";
0126 compatible = "arm,cortex-a53";
0127 reg = <0x103>;
0128 enable-method = "psci";
0129 cpu-idle-states = <&CPU_SLEEP_0>;
0130 next-level-cache = <&L2_0>;
0131 #cooling-cells = <2>;
0132 clocks = <&apcs_glb>;
0133 operating-points-v2 = <&cpu_opp_table>;
0134 power-domains = <&cpr>;
0135 power-domain-names = "cpr";
0136 };
0137 };
0138
0139 cpu_opp_table: opp-table-cpu {
0140 compatible = "operating-points-v2-kryo-cpu";
0141 opp-shared;
0142
0143 opp-1094400000 {
0144 opp-hz = /bits/ 64 <1094400000>;
0145 required-opps = <&cpr_opp1>;
0146 };
0147 opp-1248000000 {
0148 opp-hz = /bits/ 64 <1248000000>;
0149 required-opps = <&cpr_opp2>;
0150 };
0151 opp-1401600000 {
0152 opp-hz = /bits/ 64 <1401600000>;
0153 required-opps = <&cpr_opp3>;
0154 };
0155 };
0156
0157 cpr_opp_table: opp-table-cpr {
0158 compatible = "operating-points-v2-qcom-level";
0159
0160 cpr_opp1: opp1 {
0161 opp-level = <1>;
0162 qcom,opp-fuse-level = <1>;
0163 };
0164 cpr_opp2: opp2 {
0165 opp-level = <2>;
0166 qcom,opp-fuse-level = <2>;
0167 };
0168 cpr_opp3: opp3 {
0169 opp-level = <3>;
0170 qcom,opp-fuse-level = <3>;
0171 };
0172 };
0173 };
