0001 Tegra124 CPU frequency scaling driver bindings
0002 ----------------------------------------------
0003
0004 Both required and optional properties listed below must be defined
0005 under node /cpus/cpu@0.
0006
0007 Required properties:
0008 - clocks: Must contain an entry for each entry in clock-names.
0009 See ../clocks/clock-bindings.txt for details.
0010 - clock-names: Must include the following entries:
0011 - cpu_g: Clock mux for the fast CPU cluster.
0012 - pll_x: Fast PLL clocksource.
0013 - pll_p: Auxiliary PLL used during fast PLL rate changes.
0014 - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
0015
0016 Optional properties:
0017 - clock-latency: Specify the possible maximum transition latency for clock,
0018 in unit of nanoseconds.
0019
0020 Example:
0021 --------
0022 cpus {
0023 #address-cells = <1>;
0024 #size-cells = <0>;
0025
0026 cpu@0 {
0027 device_type = "cpu";
0028 compatible = "arm,cortex-a15";
0029 reg = <0>;
0030
0031 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
0032 <&tegra_car TEGRA124_CLK_PLL_X>,
0033 <&tegra_car TEGRA124_CLK_PLL_P>,
0034 <&dfll>;
0035 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
0036 clock-latency = <300000>;
0037 };
0038
0039 <...>
0040 };
