0001 Binding for MediaTek's CPUFreq driver
0002 =====================================
0003
0004 Required properties:
0005 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
0006 - clock-names: Should contain the following:
0007 "cpu" - The multiplexer for clock input of CPU cluster.
0008 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
0009 source (usually MAINPLL) when the original CPU PLL is under
0010 transition and not stable yet.
0011 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
0012 generic clock consumer properties.
0013 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
0014 for detail.
0015 - proc-supply: Regulator for Vproc of CPU cluster.
0016
0017 Optional properties:
0018 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
0019 needs to do "voltage tracking" to step by step scale up/down Vproc and
0020 Vsram to fit SoC specific needs. When absent, the voltage scaling
0021 flow is handled by hardware, hence no software "voltage tracking" is
0022 needed.
0023 - mediatek,cci:
0024 Used to confirm the link status between cpufreq and mediatek cci. Because
0025 cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
0026 To prevent the issue of high frequency and low voltage, we need to use this
0027 property to make sure mediatek cci is ready.
0028 For details of mediatek cci, please refer to
0029 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
0030 - #cooling-cells:
0031 For details, please refer to
0032 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
0033
0034 Example 1 (MT7623 SoC):
0035
0036 cpu_opp_table: opp_table {
0037 compatible = "operating-points-v2";
0038 opp-shared;
0039
0040 opp-598000000 {
0041 opp-hz = /bits/ 64 <598000000>;
0042 opp-microvolt = <1050000>;
0043 };
0044
0045 opp-747500000 {
0046 opp-hz = /bits/ 64 <747500000>;
0047 opp-microvolt = <1050000>;
0048 };
0049
0050 opp-1040000000 {
0051 opp-hz = /bits/ 64 <1040000000>;
0052 opp-microvolt = <1150000>;
0053 };
0054
0055 opp-1196000000 {
0056 opp-hz = /bits/ 64 <1196000000>;
0057 opp-microvolt = <1200000>;
0058 };
0059
0060 opp-1300000000 {
0061 opp-hz = /bits/ 64 <1300000000>;
0062 opp-microvolt = <1300000>;
0063 };
0064 };
0065
0066 cpu0: cpu@0 {
0067 device_type = "cpu";
0068 compatible = "arm,cortex-a7";
0069 reg = <0x0>;
0070 clocks = <&infracfg CLK_INFRA_CPUSEL>,
0071 <&apmixedsys CLK_APMIXED_MAINPLL>;
0072 clock-names = "cpu", "intermediate";
0073 operating-points-v2 = <&cpu_opp_table>;
0074 #cooling-cells = <2>;
0075 };
0076 cpu@1 {
0077 device_type = "cpu";
0078 compatible = "arm,cortex-a7";
0079 reg = <0x1>;
0080 operating-points-v2 = <&cpu_opp_table>;
0081 };
0082 cpu@2 {
0083 device_type = "cpu";
0084 compatible = "arm,cortex-a7";
0085 reg = <0x2>;
0086 operating-points-v2 = <&cpu_opp_table>;
0087 };
0088 cpu@3 {
0089 device_type = "cpu";
0090 compatible = "arm,cortex-a7";
0091 reg = <0x3>;
0092 operating-points-v2 = <&cpu_opp_table>;
0093 };
0094
0095 Example 2 (MT8173 SoC):
0096 cpu_opp_table_a: opp_table_a {
0097 compatible = "operating-points-v2";
0098 opp-shared;
0099
0100 opp-507000000 {
0101 opp-hz = /bits/ 64 <507000000>;
0102 opp-microvolt = <859000>;
0103 };
0104
0105 opp-702000000 {
0106 opp-hz = /bits/ 64 <702000000>;
0107 opp-microvolt = <908000>;
0108 };
0109
0110 opp-1001000000 {
0111 opp-hz = /bits/ 64 <1001000000>;
0112 opp-microvolt = <983000>;
0113 };
0114
0115 opp-1105000000 {
0116 opp-hz = /bits/ 64 <1105000000>;
0117 opp-microvolt = <1009000>;
0118 };
0119
0120 opp-1183000000 {
0121 opp-hz = /bits/ 64 <1183000000>;
0122 opp-microvolt = <1028000>;
0123 };
0124
0125 opp-1404000000 {
0126 opp-hz = /bits/ 64 <1404000000>;
0127 opp-microvolt = <1083000>;
0128 };
0129
0130 opp-1508000000 {
0131 opp-hz = /bits/ 64 <1508000000>;
0132 opp-microvolt = <1109000>;
0133 };
0134
0135 opp-1573000000 {
0136 opp-hz = /bits/ 64 <1573000000>;
0137 opp-microvolt = <1125000>;
0138 };
0139 };
0140
0141 cpu_opp_table_b: opp_table_b {
0142 compatible = "operating-points-v2";
0143 opp-shared;
0144
0145 opp-507000000 {
0146 opp-hz = /bits/ 64 <507000000>;
0147 opp-microvolt = <828000>;
0148 };
0149
0150 opp-702000000 {
0151 opp-hz = /bits/ 64 <702000000>;
0152 opp-microvolt = <867000>;
0153 };
0154
0155 opp-1001000000 {
0156 opp-hz = /bits/ 64 <1001000000>;
0157 opp-microvolt = <927000>;
0158 };
0159
0160 opp-1209000000 {
0161 opp-hz = /bits/ 64 <1209000000>;
0162 opp-microvolt = <968000>;
0163 };
0164
0165 opp-1404000000 {
0166 opp-hz = /bits/ 64 <1007000000>;
0167 opp-microvolt = <1028000>;
0168 };
0169
0170 opp-1612000000 {
0171 opp-hz = /bits/ 64 <1612000000>;
0172 opp-microvolt = <1049000>;
0173 };
0174
0175 opp-1807000000 {
0176 opp-hz = /bits/ 64 <1807000000>;
0177 opp-microvolt = <1089000>;
0178 };
0179
0180 opp-1989000000 {
0181 opp-hz = /bits/ 64 <1989000000>;
0182 opp-microvolt = <1125000>;
0183 };
0184 };
0185
0186 cpu0: cpu@0 {
0187 device_type = "cpu";
0188 compatible = "arm,cortex-a53";
0189 reg = <0x000>;
0190 enable-method = "psci";
0191 cpu-idle-states = <&CPU_SLEEP_0>;
0192 clocks = <&infracfg CLK_INFRA_CA53SEL>,
0193 <&apmixedsys CLK_APMIXED_MAINPLL>;
0194 clock-names = "cpu", "intermediate";
0195 operating-points-v2 = <&cpu_opp_table_a>;
0196 };
0197
0198 cpu1: cpu@1 {
0199 device_type = "cpu";
0200 compatible = "arm,cortex-a53";
0201 reg = <0x001>;
0202 enable-method = "psci";
0203 cpu-idle-states = <&CPU_SLEEP_0>;
0204 clocks = <&infracfg CLK_INFRA_CA53SEL>,
0205 <&apmixedsys CLK_APMIXED_MAINPLL>;
0206 clock-names = "cpu", "intermediate";
0207 operating-points-v2 = <&cpu_opp_table_a>;
0208 };
0209
0210 cpu2: cpu@100 {
0211 device_type = "cpu";
0212 compatible = "arm,cortex-a72";
0213 reg = <0x100>;
0214 enable-method = "psci";
0215 cpu-idle-states = <&CPU_SLEEP_0>;
0216 clocks = <&infracfg CLK_INFRA_CA72SEL>,
0217 <&apmixedsys CLK_APMIXED_MAINPLL>;
0218 clock-names = "cpu", "intermediate";
0219 operating-points-v2 = <&cpu_opp_table_b>;
0220 };
0221
0222 cpu3: cpu@101 {
0223 device_type = "cpu";
0224 compatible = "arm,cortex-a72";
0225 reg = <0x101>;
0226 enable-method = "psci";
0227 cpu-idle-states = <&CPU_SLEEP_0>;
0228 clocks = <&infracfg CLK_INFRA_CA72SEL>,
0229 <&apmixedsys CLK_APMIXED_MAINPLL>;
0230 clock-names = "cpu", "intermediate";
0231 operating-points-v2 = <&cpu_opp_table_b>;
0232 };
0233
0234 &cpu0 {
0235 proc-supply = <&mt6397_vpca15_reg>;
0236 };
0237
0238 &cpu1 {
0239 proc-supply = <&mt6397_vpca15_reg>;
0240 };
0241
0242 &cpu2 {
0243 proc-supply = <&da9211_vcpu_reg>;
0244 sram-supply = <&mt6397_vsramca7_reg>;
0245 };
0246
0247 &cpu3 {
0248 proc-supply = <&da9211_vcpu_reg>;
0249 sram-supply = <&mt6397_vsramca7_reg>;
0250 };
