0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MediaTek's CPUFREQ Bindings
0008
0009 maintainers:
0010 - Hector Yuan <hector.yuan@mediatek.com>
0011
0012 description:
0013 CPUFREQ HW is a hardware engine used by MediaTek SoCs to
0014 manage frequency in hardware. It is capable of controlling
0015 frequency for multiple clusters.
0016
0017 properties:
0018 compatible:
0019 const: mediatek,cpufreq-hw
0020
0021 reg:
0022 minItems: 1
0023 maxItems: 2
0024 description:
0025 Addresses and sizes for the memory of the HW bases in
0026 each frequency domain. Each entry corresponds to
0027 a register bank for each frequency domain present.
0028
0029 "#performance-domain-cells":
0030 description:
0031 Number of cells in a performance domain specifier.
0032 Set const to 1 here for nodes providing multiple
0033 performance domains.
0034 const: 1
0035
0036 required:
0037 - compatible
0038 - reg
0039 - "#performance-domain-cells"
0040
0041 additionalProperties: false
0042
0043 examples:
0044 - |
0045 cpus {
0046 #address-cells = <1>;
0047 #size-cells = <0>;
0048
0049 cpu0: cpu@0 {
0050 device_type = "cpu";
0051 compatible = "arm,cortex-a55";
0052 enable-method = "psci";
0053 performance-domains = <&performance 0>;
0054 reg = <0x000>;
0055 };
0056 };
0057
0058 /* ... */
0059
0060 soc {
0061 #address-cells = <2>;
0062 #size-cells = <2>;
0063
0064 performance: performance-controller@11bc00 {
0065 compatible = "mediatek,cpufreq-hw";
0066 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
0067
0068 #performance-domain-cells = <1>;
0069 };
0070 };
