0001 Generic cpufreq driver
0002
0003 It is a generic DT based cpufreq driver for frequency management. It supports
0004 both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share
0005 clock and voltage across all CPUs.
0006
0007 Both required and optional properties listed below must be defined
0008 under node /cpus/cpu@0.
0009
0010 Required properties:
0011 - None
0012
0013 Optional properties:
0014 - operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for
0015 details. OPPs *must* be supplied either via DT, i.e. this property, or
0016 populated at runtime.
0017 - clock-latency: Specify the possible maximum transition latency for clock,
0018 in unit of nanoseconds.
0019 - voltage-tolerance: Specify the CPU voltage tolerance in percentage.
0020 - #cooling-cells:
0021 Please refer to
0022 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.
0023
0024 Examples:
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029
0030 cpu@0 {
0031 compatible = "arm,cortex-a9";
0032 reg = <0>;
0033 next-level-cache = <&L2>;
0034 operating-points = <
0035 /* kHz uV */
0036 792000 1100000
0037 396000 950000
0038 198000 850000
0039 >;
0040 clock-latency = <61036>; /* two CLK32 periods */
0041 #cooling-cells = <2>;
0042 };
0043
0044 cpu@1 {
0045 compatible = "arm,cortex-a9";
0046 reg = <1>;
0047 next-level-cache = <&L2>;
0048 };
0049
0050 cpu@2 {
0051 compatible = "arm,cortex-a9";
0052 reg = <2>;
0053 next-level-cache = <&L2>;
0054 };
0055
0056 cpu@3 {
0057 compatible = "arm,cortex-a9";
0058 reg = <3>;
0059 next-level-cache = <&L2>;
0060 };
0061 };
