0001 Broadcom AVS mail box and interrupt register bindings
0002 =====================================================
0003
0004 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
0005 references the mailbox register used to communicate with the AVS CPU[1]. The
0006 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
0007 the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
0008 command sent to it by a driver. Interrupting the AVS CPU is mandatory for
0009 commands to be processed.
0010
0011 The interface also requires a reference to the AVS host interrupt controller,
0012 so a driver can react to interrupts generated by the AVS CPU whenever a command
0013 has been processed. See [2] for more information on the brcm,l2-intc node.
0014
0015 [1] The AVS CPU is an independent co-processor that runs proprietary
0016 firmware. On some SoCs, this firmware supports DFS and DVFS in addition to
0017 Adaptive Voltage Scaling.
0018
0019 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
0020
0021
0022 Node brcm,avs-cpu-data-mem
0023 --------------------------
0024
0025 Required properties:
0026 - compatible: must include: brcm,avs-cpu-data-mem and
0027 should include: one of brcm,bcm7271-avs-cpu-data-mem or
0028 brcm,bcm7268-avs-cpu-data-mem
0029 - reg: Specifies base physical address and size of the registers.
0030 - interrupts: The interrupt that the AVS CPU will use to interrupt the host
0031 when a command completed.
0032 - interrupt-names: The name of the interrupt used to interrupt the host.
0033
0034 Optional properties:
0035 - None
0036
0037 Node brcm,avs-cpu-l2-intr
0038 -------------------------
0039
0040 Required properties:
0041 - compatible: must include: brcm,avs-cpu-l2-intr and
0042 should include: one of brcm,bcm7271-avs-cpu-l2-intr or
0043 brcm,bcm7268-avs-cpu-l2-intr
0044 - reg: Specifies base physical address and size of the registers.
0045
0046 Optional properties:
0047 - None
0048
0049
0050 Example
0051 =======
0052
0053 avs_host_l2_intc: interrupt-controller@f04d1200 {
0054 #interrupt-cells = <1>;
0055 compatible = "brcm,l2-intc";
0056 interrupt-parent = <&intc>;
0057 reg = <0xf04d1200 0x48>;
0058 interrupt-controller;
0059 interrupts = <0x0 0x19 0x0>;
0060 interrupt-names = "avs";
0061 };
0062
0063 avs-cpu-data-mem@f04c4000 {
0064 compatible = "brcm,bcm7271-avs-cpu-data-mem",
0065 "brcm,avs-cpu-data-mem";
0066 reg = <0xf04c4000 0x60>;
0067 interrupts = <0x1a>;
0068 interrupt-parent = <&avs_host_l2_intc>;
0069 interrupt-names = "sw_intr";
0070 };
0071
0072 avs-cpu-l2-intr@f04d1100 {
0073 compatible = "brcm,bcm7271-avs-cpu-l2-intr",
0074 "brcm,avs-cpu-l2-intr";
0075 reg = <0xf04d1100 0x10>;
0076 };
