0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Idle states binding description
0008
0009 maintainers:
0010 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
0011 - Anup Patel <anup@brainfault.org>
0012
0013 description: |+
0014 ==========================================
0015 1 - Introduction
0016 ==========================================
0017
0018 ARM and RISC-V systems contain HW capable of managing power consumption
0019 dynamically, where cores can be put in different low-power states (ranging
0020 from simple wfi to power gating) according to OS PM policies. The CPU states
0021 representing the range of dynamic idle states that a processor can enter at
0022 run-time, can be specified through device tree bindings representing the
0023 parameters required to enter/exit specific idle states on a given processor.
0024
0025 ==========================================
0026 2 - ARM idle states
0027 ==========================================
0028
0029 According to the Server Base System Architecture document (SBSA, [3]), the
0030 power states an ARM CPU can be put into are identified by the following list:
0031
0032 - Running
0033 - Idle_standby
0034 - Idle_retention
0035 - Sleep
0036 - Off
0037
0038 The power states described in the SBSA document define the basic CPU states on
0039 top of which ARM platforms implement power management schemes that allow an OS
0040 PM implementation to put the processor in different idle states (which include
0041 states listed above; "off" state is not an idle state since it does not have
0042 wake-up capabilities, hence it is not considered in this document).
0043
0044 Idle state parameters (e.g. entry latency) are platform specific and need to
0045 be characterized with bindings that provide the required information to OS PM
0046 code so that it can build the required tables and use them at runtime.
0047
0048 The device tree binding definition for ARM idle states is the subject of this
0049 document.
0050
0051 ==========================================
0052 3 - RISC-V idle states
0053 ==========================================
0054
0055 On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
0056 suspend (or idle) states (ranging from simple WFI, power gating, etc). The
0057 RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
0058 standard mechanism for OS to request HART state transitions.
0059
0060 The platform specific suspend (or idle) states of a hart can be either
0061 retentive or non-rententive in nature. A retentive suspend state will
0062 preserve HART registers and CSR values for all privilege modes whereas
0063 a non-retentive suspend state will not preserve HART registers and CSR
0064 values.
0065
0066 ===========================================
0067 4 - idle-states definitions
0068 ===========================================
0069
0070 Idle states are characterized for a specific system through a set of
0071 timing and energy related properties, that underline the HW behaviour
0072 triggered upon idle states entry and exit.
0073
0074 The following diagram depicts the CPU execution phases and related timing
0075 properties required to enter and exit an idle state:
0076
0077 ..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
0078 | | | | |
0079
0080 |<------ entry ------->|
0081 | latency |
0082 |<- exit ->|
0083 | latency |
0084 |<-------- min-residency -------->|
0085 |<------- wakeup-latency ------->|
0086
0087 Diagram 1: CPU idle state execution phases
0088
0089 EXEC: Normal CPU execution.
0090
0091 PREP: Preparation phase before committing the hardware to idle mode
0092 like cache flushing. This is abortable on pending wake-up
0093 event conditions. The abort latency is assumed to be negligible
0094 (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
0095 goes back to EXEC. This phase is optional. If not abortable,
0096 this should be included in the ENTRY phase instead.
0097
0098 ENTRY: The hardware is committed to idle mode. This period must run
0099 to completion up to IDLE before anything else can happen.
0100
0101 IDLE: This is the actual energy-saving idle period. This may last
0102 between 0 and infinite time, until a wake-up event occurs.
0103
0104 EXIT: Period during which the CPU is brought back to operational
0105 mode (EXEC).
0106
0107 entry-latency: Worst case latency required to enter the idle state. The
0108 exit-latency may be guaranteed only after entry-latency has passed.
0109
0110 min-residency: Minimum period, including preparation and entry, for a given
0111 idle state to be worthwhile energywise.
0112
0113 wakeup-latency: Maximum delay between the signaling of a wake-up event and the
0114 CPU being able to execute normal code again. If not specified, this is assumed
0115 to be entry-latency + exit-latency.
0116
0117 These timing parameters can be used by an OS in different circumstances.
0118
0119 An idle CPU requires the expected min-residency time to select the most
0120 appropriate idle state based on the expected expiry time of the next IRQ
0121 (i.e. wake-up) that causes the CPU to return to the EXEC phase.
0122
0123 An operating system scheduler may need to compute the shortest wake-up delay
0124 for CPUs in the system by detecting how long will it take to get a CPU out
0125 of an idle state, e.g.:
0126
0127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
0128
0129 In other words, the scheduler can make its scheduling decision by selecting
0130 (e.g. waking-up) the CPU with the shortest wake-up delay.
0131 The wake-up delay must take into account the entry latency if that period
0132 has not expired. The abortable nature of the PREP period can be ignored
0133 if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
0134 the worst case since it depends on the CPU operating conditions, i.e. caches
0135 state).
0136
0137 An OS has to reliably probe the wakeup-latency since some devices can enforce
0138 latency constraint guarantees to work properly, so the OS has to detect the
0139 worst case wake-up latency it can incur if a CPU is allowed to enter an
0140 idle state, and possibly to prevent that to guarantee reliable device
0141 functioning.
0142
0143 The min-residency time parameter deserves further explanation since it is
0144 expressed in time units but must factor in energy consumption coefficients.
0145
0146 The energy consumption of a cpu when it enters a power state can be roughly
0147 characterised by the following graph:
0148
0149 |
0150 |
0151 |
0152 e |
0153 n | /---
0154 e | /------
0155 r | /------
0156 g | /-----
0157 y | /------
0158 | ----
0159 | /|
0160 | / |
0161 | / |
0162 | / |
0163 | / |
0164 | / |
0165 |/ |
0166 -----|-------+----------------------------------
0167 0| 1 time(ms)
0168
0169 Graph 1: Energy vs time example
0170
0171 The graph is split in two parts delimited by time 1ms on the X-axis.
0172 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
0173 and denotes the energy costs incurred while entering and leaving the idle
0174 state.
0175 The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
0176 shallower slope and essentially represents the energy consumption of the idle
0177 state.
0178
0179 min-residency is defined for a given idle state as the minimum expected
0180 residency time for a state (inclusive of preparation and entry) after
0181 which choosing that state become the most energy efficient option. A good
0182 way to visualise this, is by taking the same graph above and comparing some
0183 states energy consumptions plots.
0184
0185 For sake of simplicity, let's consider a system with two idle states IDLE1,
0186 and IDLE2:
0187
0188 |
0189 |
0190 |
0191 | /-- IDLE1
0192 e | /---
0193 n | /----
0194 e | /---
0195 r | /-----/--------- IDLE2
0196 g | /-------/---------
0197 y | ------------ /---|
0198 | / /---- |
0199 | / /--- |
0200 | / /---- |
0201 | / /--- |
0202 | --- |
0203 | / |
0204 | / |
0205 |/ | time
0206 ---/----------------------------+------------------------
0207 |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
0208 |
0209 IDLE2-min-residency
0210
0211 Graph 2: idle states min-residency example
0212
0213 In graph 2 above, that takes into account idle states entry/exit energy
0214 costs, it is clear that if the idle state residency time (i.e. time till next
0215 wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
0216 choice energywise.
0217
0218 This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
0219 than IDLE2.
0220
0221 However, the lower power consumption (i.e. shallower energy curve slope) of
0222 idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
0223 efficient.
0224
0225 The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
0226 shallower states in a system with multiple idle states) is defined
0227 IDLE2-min-residency and corresponds to the time when energy consumption of
0228 IDLE1 and IDLE2 states breaks even.
0229
0230 The definitions provided in this section underpin the idle states
0231 properties specification that is the subject of the following sections.
0232
0233 ===========================================
0234 5 - idle-states node
0235 ===========================================
0236
0237 The processor idle states are defined within the idle-states node, which is
0238 a direct child of the cpus node [1] and provides a container where the
0239 processor idle states, defined as device tree nodes, are listed.
0240
0241 On ARM systems, it is a container of processor idle states nodes. If the
0242 system does not provide CPU power management capabilities, or the processor
0243 just supports idle_standby, an idle-states node is not required.
0244
0245 ===========================================
0246 6 - References
0247 ===========================================
0248
0249 [1] ARM Linux Kernel documentation - CPUs bindings
0250 Documentation/devicetree/bindings/arm/cpus.yaml
0251
0252 [2] ARM Linux Kernel documentation - PSCI bindings
0253 Documentation/devicetree/bindings/arm/psci.yaml
0254
0255 [3] ARM Server Base System Architecture (SBSA)
0256 http://infocenter.arm.com/help/index.jsp
0257
0258 [4] ARM Architecture Reference Manuals
0259 http://infocenter.arm.com/help/index.jsp
0260
0261 [5] ARM Linux Kernel documentation - Booting AArch64 Linux
0262 Documentation/arm64/booting.rst
0263
0264 [6] RISC-V Linux Kernel documentation - CPUs bindings
0265 Documentation/devicetree/bindings/riscv/cpus.yaml
0266
0267 [7] RISC-V Supervisor Binary Interface (SBI)
0268 http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
0269
0270 properties:
0271 $nodename:
0272 const: idle-states
0273
0274 entry-method:
0275 description: |
0276 Usage and definition depend on ARM architecture version.
0277
0278 On ARM v8 64-bit this property is required.
0279 On ARM 32-bit systems this property is optional
0280
0281 This assumes that the "enable-method" property is set to "psci" in the cpu
0282 node[5] that is responsible for setting up CPU idle management in the OS
0283 implementation.
0284 const: psci
0285
0286 patternProperties:
0287 "^(cpu|cluster)-":
0288 type: object
0289 description: |
0290 Each state node represents an idle state description and must be defined
0291 as follows.
0292
0293 The idle state entered by executing the wfi instruction (idle_standby
0294 SBSA,[3][4]) is considered standard on all ARM and RISC-V platforms and
0295 therefore must not be listed.
0296
0297 In addition to the properties listed above, a state node may require
0298 additional properties specific to the entry-method defined in the
0299 idle-states node. Please refer to the entry-method bindings
0300 documentation for properties definitions.
0301
0302 properties:
0303 compatible:
0304 enum:
0305 - arm,idle-state
0306 - riscv,idle-state
0307
0308 arm,psci-suspend-param:
0309 $ref: /schemas/types.yaml#/definitions/uint32
0310 description: |
0311 power_state parameter to pass to the ARM PSCI suspend call.
0312
0313 Device tree nodes that require usage of PSCI CPU_SUSPEND function
0314 (i.e. idle states node with entry-method property is set to "psci")
0315 must specify this property.
0316
0317 riscv,sbi-suspend-param:
0318 $ref: /schemas/types.yaml#/definitions/uint32
0319 description: |
0320 suspend_type parameter to pass to the RISC-V SBI HSM suspend call.
0321
0322 This property is required in idle state nodes of device tree meant
0323 for RISC-V systems. For more details on the suspend_type parameter
0324 refer the SBI specifiation v0.3 (or higher) [7].
0325
0326 local-timer-stop:
0327 description:
0328 If present the CPU local timer control logic is
0329 lost on state entry, otherwise it is retained.
0330 type: boolean
0331
0332 entry-latency-us:
0333 description:
0334 Worst case latency in microseconds required to enter the idle state.
0335
0336 exit-latency-us:
0337 description:
0338 Worst case latency in microseconds required to exit the idle state.
0339 The exit-latency-us duration may be guaranteed only after
0340 entry-latency-us has passed.
0341
0342 min-residency-us:
0343 description:
0344 Minimum residency duration in microseconds, inclusive of preparation
0345 and entry, for this idle state to be considered worthwhile energy wise
0346 (refer to section 2 of this document for a complete description).
0347
0348 wakeup-latency-us:
0349 description: |
0350 Maximum delay between the signaling of a wake-up event and the CPU
0351 being able to execute normal code again. If omitted, this is assumed
0352 to be equal to:
0353
0354 entry-latency-us + exit-latency-us
0355
0356 It is important to supply this value on systems where the duration of
0357 PREP phase (see diagram 1, section 2) is non-neglibigle. In such
0358 systems entry-latency-us + exit-latency-us will exceed
0359 wakeup-latency-us by this duration.
0360
0361 idle-state-name:
0362 $ref: /schemas/types.yaml#/definitions/string
0363 description:
0364 A string used as a descriptive name for the idle state.
0365
0366 additionalProperties: false
0367
0368 required:
0369 - compatible
0370 - entry-latency-us
0371 - exit-latency-us
0372 - min-residency-us
0373
0374 additionalProperties: false
0375
0376 examples:
0377 - |
0378
0379 cpus {
0380 #size-cells = <0>;
0381 #address-cells = <2>;
0382
0383 cpu@0 {
0384 device_type = "cpu";
0385 compatible = "arm,cortex-a57";
0386 reg = <0x0 0x0>;
0387 enable-method = "psci";
0388 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
0389 <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
0390 };
0391
0392 cpu@1 {
0393 device_type = "cpu";
0394 compatible = "arm,cortex-a57";
0395 reg = <0x0 0x1>;
0396 enable-method = "psci";
0397 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
0398 <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
0399 };
0400
0401 cpu@100 {
0402 device_type = "cpu";
0403 compatible = "arm,cortex-a57";
0404 reg = <0x0 0x100>;
0405 enable-method = "psci";
0406 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
0407 <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
0408 };
0409
0410 cpu@101 {
0411 device_type = "cpu";
0412 compatible = "arm,cortex-a57";
0413 reg = <0x0 0x101>;
0414 enable-method = "psci";
0415 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
0416 <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
0417 };
0418
0419 cpu@10000 {
0420 device_type = "cpu";
0421 compatible = "arm,cortex-a57";
0422 reg = <0x0 0x10000>;
0423 enable-method = "psci";
0424 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
0425 <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
0426 };
0427
0428 cpu@10001 {
0429 device_type = "cpu";
0430 compatible = "arm,cortex-a57";
0431 reg = <0x0 0x10001>;
0432 enable-method = "psci";
0433 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
0434 <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
0435 };
0436
0437 cpu@10100 {
0438 device_type = "cpu";
0439 compatible = "arm,cortex-a57";
0440 reg = <0x0 0x10100>;
0441 enable-method = "psci";
0442 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
0443 <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
0444 };
0445
0446 cpu@10101 {
0447 device_type = "cpu";
0448 compatible = "arm,cortex-a57";
0449 reg = <0x0 0x10101>;
0450 enable-method = "psci";
0451 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
0452 <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
0453 };
0454
0455 cpu@100000000 {
0456 device_type = "cpu";
0457 compatible = "arm,cortex-a53";
0458 reg = <0x1 0x0>;
0459 enable-method = "psci";
0460 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
0461 <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
0462 };
0463
0464 cpu@100000001 {
0465 device_type = "cpu";
0466 compatible = "arm,cortex-a53";
0467 reg = <0x1 0x1>;
0468 enable-method = "psci";
0469 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
0470 <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
0471 };
0472
0473 cpu@100000100 {
0474 device_type = "cpu";
0475 compatible = "arm,cortex-a53";
0476 reg = <0x1 0x100>;
0477 enable-method = "psci";
0478 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
0479 <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
0480 };
0481
0482 cpu@100000101 {
0483 device_type = "cpu";
0484 compatible = "arm,cortex-a53";
0485 reg = <0x1 0x101>;
0486 enable-method = "psci";
0487 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
0488 <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
0489 };
0490
0491 cpu@100010000 {
0492 device_type = "cpu";
0493 compatible = "arm,cortex-a53";
0494 reg = <0x1 0x10000>;
0495 enable-method = "psci";
0496 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
0497 <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
0498 };
0499
0500 cpu@100010001 {
0501 device_type = "cpu";
0502 compatible = "arm,cortex-a53";
0503 reg = <0x1 0x10001>;
0504 enable-method = "psci";
0505 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
0506 <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
0507 };
0508
0509 cpu@100010100 {
0510 device_type = "cpu";
0511 compatible = "arm,cortex-a53";
0512 reg = <0x1 0x10100>;
0513 enable-method = "psci";
0514 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
0515 <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
0516 };
0517
0518 cpu@100010101 {
0519 device_type = "cpu";
0520 compatible = "arm,cortex-a53";
0521 reg = <0x1 0x10101>;
0522 enable-method = "psci";
0523 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
0524 <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
0525 };
0526
0527 idle-states {
0528 entry-method = "psci";
0529
0530 CPU_RETENTION_0_0: cpu-retention-0-0 {
0531 compatible = "arm,idle-state";
0532 arm,psci-suspend-param = <0x0010000>;
0533 entry-latency-us = <20>;
0534 exit-latency-us = <40>;
0535 min-residency-us = <80>;
0536 };
0537
0538 CLUSTER_RETENTION_0: cluster-retention-0 {
0539 compatible = "arm,idle-state";
0540 local-timer-stop;
0541 arm,psci-suspend-param = <0x1010000>;
0542 entry-latency-us = <50>;
0543 exit-latency-us = <100>;
0544 min-residency-us = <250>;
0545 wakeup-latency-us = <130>;
0546 };
0547
0548 CPU_SLEEP_0_0: cpu-sleep-0-0 {
0549 compatible = "arm,idle-state";
0550 local-timer-stop;
0551 arm,psci-suspend-param = <0x0010000>;
0552 entry-latency-us = <250>;
0553 exit-latency-us = <500>;
0554 min-residency-us = <950>;
0555 };
0556
0557 CLUSTER_SLEEP_0: cluster-sleep-0 {
0558 compatible = "arm,idle-state";
0559 local-timer-stop;
0560 arm,psci-suspend-param = <0x1010000>;
0561 entry-latency-us = <600>;
0562 exit-latency-us = <1100>;
0563 min-residency-us = <2700>;
0564 wakeup-latency-us = <1500>;
0565 };
0566
0567 CPU_RETENTION_1_0: cpu-retention-1-0 {
0568 compatible = "arm,idle-state";
0569 arm,psci-suspend-param = <0x0010000>;
0570 entry-latency-us = <20>;
0571 exit-latency-us = <40>;
0572 min-residency-us = <90>;
0573 };
0574
0575 CLUSTER_RETENTION_1: cluster-retention-1 {
0576 compatible = "arm,idle-state";
0577 local-timer-stop;
0578 arm,psci-suspend-param = <0x1010000>;
0579 entry-latency-us = <50>;
0580 exit-latency-us = <100>;
0581 min-residency-us = <270>;
0582 wakeup-latency-us = <100>;
0583 };
0584
0585 CPU_SLEEP_1_0: cpu-sleep-1-0 {
0586 compatible = "arm,idle-state";
0587 local-timer-stop;
0588 arm,psci-suspend-param = <0x0010000>;
0589 entry-latency-us = <70>;
0590 exit-latency-us = <100>;
0591 min-residency-us = <300>;
0592 wakeup-latency-us = <150>;
0593 };
0594
0595 CLUSTER_SLEEP_1: cluster-sleep-1 {
0596 compatible = "arm,idle-state";
0597 local-timer-stop;
0598 arm,psci-suspend-param = <0x1010000>;
0599 entry-latency-us = <500>;
0600 exit-latency-us = <1200>;
0601 min-residency-us = <3500>;
0602 wakeup-latency-us = <1300>;
0603 };
0604 };
0605 };
0606
0607 - |
0608 // Example 2 (ARM 32-bit, 8-cpu system, two clusters):
0609
0610 cpus {
0611 #size-cells = <0>;
0612 #address-cells = <1>;
0613
0614 cpu@0 {
0615 device_type = "cpu";
0616 compatible = "arm,cortex-a15";
0617 reg = <0x0>;
0618 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
0619 };
0620
0621 cpu@1 {
0622 device_type = "cpu";
0623 compatible = "arm,cortex-a15";
0624 reg = <0x1>;
0625 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
0626 };
0627
0628 cpu@2 {
0629 device_type = "cpu";
0630 compatible = "arm,cortex-a15";
0631 reg = <0x2>;
0632 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
0633 };
0634
0635 cpu@3 {
0636 device_type = "cpu";
0637 compatible = "arm,cortex-a15";
0638 reg = <0x3>;
0639 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
0640 };
0641
0642 cpu@100 {
0643 device_type = "cpu";
0644 compatible = "arm,cortex-a7";
0645 reg = <0x100>;
0646 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
0647 };
0648
0649 cpu@101 {
0650 device_type = "cpu";
0651 compatible = "arm,cortex-a7";
0652 reg = <0x101>;
0653 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
0654 };
0655
0656 cpu@102 {
0657 device_type = "cpu";
0658 compatible = "arm,cortex-a7";
0659 reg = <0x102>;
0660 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
0661 };
0662
0663 cpu@103 {
0664 device_type = "cpu";
0665 compatible = "arm,cortex-a7";
0666 reg = <0x103>;
0667 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
0668 };
0669
0670 idle-states {
0671 cpu_sleep_0_0: cpu-sleep-0-0 {
0672 compatible = "arm,idle-state";
0673 local-timer-stop;
0674 entry-latency-us = <200>;
0675 exit-latency-us = <100>;
0676 min-residency-us = <400>;
0677 wakeup-latency-us = <250>;
0678 };
0679
0680 cluster_sleep_0: cluster-sleep-0 {
0681 compatible = "arm,idle-state";
0682 local-timer-stop;
0683 entry-latency-us = <500>;
0684 exit-latency-us = <1500>;
0685 min-residency-us = <2500>;
0686 wakeup-latency-us = <1700>;
0687 };
0688
0689 cpu_sleep_1_0: cpu-sleep-1-0 {
0690 compatible = "arm,idle-state";
0691 local-timer-stop;
0692 entry-latency-us = <300>;
0693 exit-latency-us = <500>;
0694 min-residency-us = <900>;
0695 wakeup-latency-us = <600>;
0696 };
0697
0698 cluster_sleep_1: cluster-sleep-1 {
0699 compatible = "arm,idle-state";
0700 local-timer-stop;
0701 entry-latency-us = <800>;
0702 exit-latency-us = <2000>;
0703 min-residency-us = <6500>;
0704 wakeup-latency-us = <2300>;
0705 };
0706 };
0707 };
0708
0709 - |
0710 // Example 3 (RISC-V 64-bit, 4-cpu systems, two clusters):
0711
0712 cpus {
0713 #size-cells = <0>;
0714 #address-cells = <1>;
0715
0716 cpu@0 {
0717 device_type = "cpu";
0718 compatible = "riscv";
0719 reg = <0x0>;
0720 riscv,isa = "rv64imafdc";
0721 mmu-type = "riscv,sv48";
0722 cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
0723 <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
0724
0725 cpu_intc0: interrupt-controller {
0726 #interrupt-cells = <1>;
0727 compatible = "riscv,cpu-intc";
0728 interrupt-controller;
0729 };
0730 };
0731
0732 cpu@1 {
0733 device_type = "cpu";
0734 compatible = "riscv";
0735 reg = <0x1>;
0736 riscv,isa = "rv64imafdc";
0737 mmu-type = "riscv,sv48";
0738 cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
0739 <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
0740
0741 cpu_intc1: interrupt-controller {
0742 #interrupt-cells = <1>;
0743 compatible = "riscv,cpu-intc";
0744 interrupt-controller;
0745 };
0746 };
0747
0748 cpu@10 {
0749 device_type = "cpu";
0750 compatible = "riscv";
0751 reg = <0x10>;
0752 riscv,isa = "rv64imafdc";
0753 mmu-type = "riscv,sv48";
0754 cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
0755 <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
0756
0757 cpu_intc10: interrupt-controller {
0758 #interrupt-cells = <1>;
0759 compatible = "riscv,cpu-intc";
0760 interrupt-controller;
0761 };
0762 };
0763
0764 cpu@11 {
0765 device_type = "cpu";
0766 compatible = "riscv";
0767 reg = <0x11>;
0768 riscv,isa = "rv64imafdc";
0769 mmu-type = "riscv,sv48";
0770 cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
0771 <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
0772
0773 cpu_intc11: interrupt-controller {
0774 #interrupt-cells = <1>;
0775 compatible = "riscv,cpu-intc";
0776 interrupt-controller;
0777 };
0778 };
0779
0780 idle-states {
0781 CPU_RET_0_0: cpu-retentive-0-0 {
0782 compatible = "riscv,idle-state";
0783 riscv,sbi-suspend-param = <0x10000000>;
0784 entry-latency-us = <20>;
0785 exit-latency-us = <40>;
0786 min-residency-us = <80>;
0787 };
0788
0789 CPU_NONRET_0_0: cpu-nonretentive-0-0 {
0790 compatible = "riscv,idle-state";
0791 riscv,sbi-suspend-param = <0x90000000>;
0792 entry-latency-us = <250>;
0793 exit-latency-us = <500>;
0794 min-residency-us = <950>;
0795 };
0796
0797 CLUSTER_RET_0: cluster-retentive-0 {
0798 compatible = "riscv,idle-state";
0799 riscv,sbi-suspend-param = <0x11000000>;
0800 local-timer-stop;
0801 entry-latency-us = <50>;
0802 exit-latency-us = <100>;
0803 min-residency-us = <250>;
0804 wakeup-latency-us = <130>;
0805 };
0806
0807 CLUSTER_NONRET_0: cluster-nonretentive-0 {
0808 compatible = "riscv,idle-state";
0809 riscv,sbi-suspend-param = <0x91000000>;
0810 local-timer-stop;
0811 entry-latency-us = <600>;
0812 exit-latency-us = <1100>;
0813 min-residency-us = <2700>;
0814 wakeup-latency-us = <1500>;
0815 };
0816
0817 CPU_RET_1_0: cpu-retentive-1-0 {
0818 compatible = "riscv,idle-state";
0819 riscv,sbi-suspend-param = <0x10000010>;
0820 entry-latency-us = <20>;
0821 exit-latency-us = <40>;
0822 min-residency-us = <80>;
0823 };
0824
0825 CPU_NONRET_1_0: cpu-nonretentive-1-0 {
0826 compatible = "riscv,idle-state";
0827 riscv,sbi-suspend-param = <0x90000010>;
0828 entry-latency-us = <250>;
0829 exit-latency-us = <500>;
0830 min-residency-us = <950>;
0831 };
0832
0833 CLUSTER_RET_1: cluster-retentive-1 {
0834 compatible = "riscv,idle-state";
0835 riscv,sbi-suspend-param = <0x11000010>;
0836 local-timer-stop;
0837 entry-latency-us = <50>;
0838 exit-latency-us = <100>;
0839 min-residency-us = <250>;
0840 wakeup-latency-us = <130>;
0841 };
0842
0843 CLUSTER_NONRET_1: cluster-nonretentive-1 {
0844 compatible = "riscv,idle-state";
0845 riscv,sbi-suspend-param = <0x91000010>;
0846 local-timer-stop;
0847 entry-latency-us = <600>;
0848 exit-latency-us = <1100>;
0849 min-residency-us = <2700>;
0850 wakeup-latency-us = <1500>;
0851 };
0852 };
0853 };
0854
0855 ...
