bindings/clock/zynq-7000.txt

0001 Device Tree Clock bindings for the Zynq 7000 EPP
0002
0003 The Zynq EPP has several different clk providers, each with there own bindings.
0004 The purpose of this document is to document their usage.
0005
0006 See clock_bindings.txt for more information on the generic clock bindings.
0007 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
0008
0009 == Clock Controller ==
0010 The clock controller is a logical abstraction of Zynq's clock tree. It reads
0011 required input clock frequencies from the devicetree and acts as clock provider
0012 for all clock consumers of PS clocks.
0013
0014 Required properties:
0015  - #clock-cells : Must be 1
0016  - compatible : "xlnx,ps7-clkc"
0017  - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
0018  - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
0019                       (usually 33 MHz oscillators are used for Zynq platforms)
0020  - clock-output-names : List of strings used to name the clock outputs. Shall be
0021                         a list of the outputs given below.
0022
0023 Optional properties:
0024  - clocks : as described in the clock bindings
0025  - clock-names : as described in the clock bindings
0026  - fclk-enable : Bit mask to enable FCLKs statically at boot time.
0027                  Bit [0..3] correspond to FCLK0..FCLK3. The corresponding
0028                  FCLK will only be enabled if it is actually running at
0029                  boot time.
0030
0031 Clock inputs:
0032 The following strings are optional parameters to the 'clock-names' property in
0033 order to provide an optional (E)MIO clock source.
0034  - swdt_ext_clk
0035  - gem0_emio_clk
0036  - gem1_emio_clk
0037  - mio_clk_XX           # with XX = 00..53
0038 ...
0039
0040 Clock outputs:
0041  0:  armpll
0042  1:  ddrpll
0043  2:  iopll
0044  3:  cpu_6or4x
0045  4:  cpu_3or2x
0046  5:  cpu_2x
0047  6:  cpu_1x
0048  7:  ddr2x
0049  8:  ddr3x
0050  9:  dci
0051  10: lqspi
0052  11: smc
0053  12: pcap
0054  13: gem0
0055  14: gem1
0056  15: fclk0
0057  16: fclk1
0058  17: fclk2
0059  18: fclk3
0060  19: can0
0061  20: can1
0062  21: sdio0
0063  22: sdio1
0064  23: uart0
0065  24: uart1
0066  25: spi0
0067  26: spi1
0068  27: dma
0069  28: usb0_aper
0070  29: usb1_aper
0071  30: gem0_aper
0072  31: gem1_aper
0073  32: sdio0_aper
0074  33: sdio1_aper
0075  34: spi0_aper
0076  35: spi1_aper
0077  36: can0_aper
0078  37: can1_aper
0079  38: i2c0_aper
0080  39: i2c1_aper
0081  40: uart0_aper
0082  41: uart1_aper
0083  42: gpio_aper
0084  43: lqspi_aper
0085  44: smc_aper
0086  45: swdt
0087  46: dbg_trc
0088  47: dbg_apb
0089
0090 Example:
0091         clkc: clkc@100 {
0092                 #clock-cells = <1>;
0093                 compatible = "xlnx,ps7-clkc";
0094                 ps-clk-frequency = <33333333>;
0095                 reg = <0x100 0x100>;
0096                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
0097                                 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
0098                                 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
0099                                 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
0100                                 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
0101                                 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
0102                                 "gem1_aper", "sdio0_aper", "sdio1_aper",
0103                                 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
0104                                 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
0105                                 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
0106                                 "dbg_trc", "dbg_apb";
0107                 # optional props
0108                 clocks = <&clkc 16>, <&clk_foo>;
0109                 clock-names = "gem1_emio_clk", "can_mio_clk_23";
0110         };