0001 --------------------------------------------------------------------------
0002 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
0003 Zynq MPSoC firmware interface
0004 --------------------------------------------------------------------------
0005 The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
0006 tree. It reads required input clock frequencies from the devicetree and acts
0007 as clock provider for all clock consumers of PS clocks.
0008
0009 See clock_bindings.txt for more information on the generic clock bindings.
0010
0011 Required properties:
0012 - #clock-cells: Must be 1
0013 - compatible: Must contain: "xlnx,zynqmp-clk"
0014 - clocks: List of clock specifiers which are external input
0015 clocks to the given clock controller. Please refer
0016 the next section to find the input clocks for a
0017 given controller.
0018 - clock-names: List of clock names which are exteral input clocks
0019 to the given clock controller. Please refer to the
0020 clock bindings for more details.
0021
0022 Input clocks for zynqmp Ultrascale+ clock controller:
0023
0024 The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
0025 inputs. These required clock inputs are:
0026 - pss_ref_clk (PS reference clock)
0027 - video_clk (reference clock for video system )
0028 - pss_alt_ref_clk (alternative PS reference clock)
0029 - aux_ref_clk
0030 - gt_crx_ref_clk (transceiver reference clock)
0031
0032 The following strings are optional parameters to the 'clock-names' property in
0033 order to provide an optional (E)MIO clock source:
0034 - swdt0_ext_clk
0035 - swdt1_ext_clk
0036 - gem0_emio_clk
0037 - gem1_emio_clk
0038 - gem2_emio_clk
0039 - gem3_emio_clk
0040 - mio_clk_XX # with XX = 00..77
0041 - mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
0042
0043
0044 Output clocks are registered based on clock information received
0045 from firmware. Output clocks indexes are mentioned in
0046 include/dt-bindings/clock/xlnx-zynqmp-clk.h.
0047
0048 -------
0049 Example
0050 -------
0051
0052 firmware {
0053 zynqmp_firmware: zynqmp-firmware {
0054 compatible = "xlnx,zynqmp-firmware";
0055 method = "smc";
0056 zynqmp_clk: clock-controller {
0057 #clock-cells = <1>;
0058 compatible = "xlnx,zynqmp-clk";
0059 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
0060 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
0061 };
0062 };
0063 };
