0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Xilinx Versal clock controller
0008
0009 maintainers:
0010 - Michal Simek <michal.simek@xilinx.com>
0011 - Jolly Shah <jolly.shah@xilinx.com>
0012 - Rajan Vaja <rajan.vaja@xilinx.com>
0013
0014 description: |
0015 The clock controller is a hardware block of Xilinx versal clock tree. It
0016 reads required input clock frequencies from the devicetree and acts as clock
0017 provider for all clock consumers of PS clocks.
0018
0019 select: false
0020
0021 properties:
0022 compatible:
0023 const: xlnx,versal-clk
0024
0025 "#clock-cells":
0026 const: 1
0027
0028 clocks:
0029 description: List of clock specifiers which are external input
0030 clocks to the given clock controller.
0031 items:
0032 - description: reference clock
0033 - description: alternate reference clock
0034 - description: alternate reference clock for programmable logic
0035
0036 clock-names:
0037 items:
0038 - const: ref
0039 - const: alt_ref
0040 - const: pl_alt_ref
0041
0042 required:
0043 - compatible
0044 - "#clock-cells"
0045 - clocks
0046 - clock-names
0047
0048 additionalProperties: false
0049
0050 examples:
0051 - |
0052 firmware {
0053 zynqmp_firmware: zynqmp-firmware {
0054 compatible = "xlnx,zynqmp-firmware";
0055 method = "smc";
0056 versal_clk: clock-controller {
0057 #clock-cells = <1>;
0058 compatible = "xlnx,versal-clk";
0059 clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
0060 clock-names = "ref", "alt_ref", "pl_alt_ref";
0061 };
0062 };
0063 };
0064 ...
