0001 Device Tree Clock bindings for APM X-Gene
0002
0003 This binding uses the common clock binding[1].
0004
0005 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0006
0007 Required properties:
0008 - compatible : shall be one of the following:
0009 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
0010 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
0011 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
0012 "apm,xgene-device-clock" - for a X-Gene device clock
0013 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
0014 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
0015
0016 Required properties for SoC or PCP PLL clocks:
0017 - reg : shall be the physical PLL register address for the pll clock.
0018 - clocks : shall be the input parent clock phandle for the clock. This should
0019 be the reference clock.
0020 - #clock-cells : shall be set to 1.
0021 - clock-output-names : shall be the name of the PLL referenced by derive
0022 clock.
0023 Optional properties for PLL clocks:
0024 - clock-names : shall be the name of the PLL. If missing, use the device name.
0025
0026 Required properties for PMD clocks:
0027 - reg : shall be the physical register address for the pmd clock.
0028 - clocks : shall be the input parent clock phandle for the clock.
0029 - #clock-cells : shall be set to 1.
0030 - clock-output-names : shall be the name of the clock referenced by derive
0031 clock.
0032 Optional properties for PLL clocks:
0033 - clock-names : shall be the name of the clock. If missing, use the device name.
0034
0035 Required properties for device clocks:
0036 - reg : shall be a list of address and length pairs describing the CSR
0037 reset and/or the divider. Either may be omitted, but at least
0038 one must be present.
0039 - reg-names : shall be a string list describing the reg resource. This
0040 may include "csr-reg" and/or "div-reg". If this property
0041 is not present, the reg property is assumed to describe
0042 only "csr-reg".
0043 - clocks : shall be the input parent clock phandle for the clock.
0044 - #clock-cells : shall be set to 1.
0045 - clock-output-names : shall be the name of the device referenced.
0046 Optional properties for device clocks:
0047 - clock-names : shall be the name of the device clock. If missing, use the
0048 device name.
0049 - csr-offset : Offset to the CSR reset register from the reset address base.
0050 Default is 0.
0051 - csr-mask : CSR reset mask bit. Default is 0xF.
0052 - enable-offset : Offset to the enable register from the reset address base.
0053 Default is 0x8.
0054 - enable-mask : CSR enable mask bit. Default is 0xF.
0055 - divider-offset : Offset to the divider CSR register from the divider base.
0056 Default is 0x0.
0057 - divider-width : Width of the divider register. Default is 0.
0058 - divider-shift : Bit shift of the divider register. Default is 0.
0059
0060 For example:
0061
0062 pcppll: pcppll@17000100 {
0063 compatible = "apm,xgene-pcppll-clock";
0064 #clock-cells = <1>;
0065 clocks = <&refclk 0>;
0066 clock-names = "pcppll";
0067 reg = <0x0 0x17000100 0x0 0x1000>;
0068 clock-output-names = "pcppll";
0069 type = <0>;
0070 };
0071
0072 pmd0clk: pmd0clk@7e200200 {
0073 compatible = "apm,xgene-pmd-clock";
0074 #clock-cells = <1>;
0075 clocks = <&pmdpll 0>;
0076 reg = <0x0 0x7e200200 0x0 0x10>;
0077 clock-output-names = "pmd0clk";
0078 };
0079
0080 socpll: socpll@17000120 {
0081 compatible = "apm,xgene-socpll-clock";
0082 #clock-cells = <1>;
0083 clocks = <&refclk 0>;
0084 clock-names = "socpll";
0085 reg = <0x0 0x17000120 0x0 0x1000>;
0086 clock-output-names = "socpll";
0087 type = <1>;
0088 };
0089
0090 qmlclk: qmlclk {
0091 compatible = "apm,xgene-device-clock";
0092 #clock-cells = <1>;
0093 clocks = <&socplldiv2 0>;
0094 clock-names = "qmlclk";
0095 reg = <0x0 0x1703C000 0x0 0x1000>;
0096 reg-name = "csr-reg";
0097 clock-output-names = "qmlclk";
0098 };
0099
0100 ethclk: ethclk {
0101 compatible = "apm,xgene-device-clock";
0102 #clock-cells = <1>;
0103 clocks = <&socplldiv2 0>;
0104 clock-names = "ethclk";
0105 reg = <0x0 0x17000000 0x0 0x1000>;
0106 reg-names = "div-reg";
0107 divider-offset = <0x238>;
0108 divider-width = <0x9>;
0109 divider-shift = <0x0>;
0110 clock-output-names = "ethclk";
0111 };
0112
0113 apbclk: apbclk {
0114 compatible = "apm,xgene-device-clock";
0115 #clock-cells = <1>;
0116 clocks = <&ahbclk 0>;
0117 clock-names = "apbclk";
0118 reg = <0x0 0x1F2AC000 0x0 0x1000
0119 0x0 0x1F2AC000 0x0 0x1000>;
0120 reg-names = "csr-reg", "div-reg";
0121 csr-offset = <0x0>;
0122 csr-mask = <0x200>;
0123 enable-offset = <0x8>;
0124 enable-mask = <0x200>;
0125 divider-offset = <0x10>;
0126 divider-width = <0x2>;
0127 divider-shift = <0x0>;
0128 flags = <0x8>;
0129 clock-output-names = "apbclk";
0130 };
0131
