0001 Device Tree Clock bindings for arch-vt8500
0002
0003 This binding uses the common clock binding[1].
0004
0005 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0006
0007 Required properties:
0008 - compatible : shall be one of the following:
0009 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
0010 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
0011 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
0012 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
0013 "via,vt8500-device-clock" - for a VT/WM device clock
0014
0015 Required properties for PLL clocks:
0016 - reg : shall be the control register offset from PMC base for the pll clock.
0017 - clocks : shall be the input parent clock phandle for the clock. This should
0018 be the reference clock.
0019 - #clock-cells : from common clock binding; shall be set to 0.
0020
0021 Required properties for device clocks:
0022 - clocks : shall be the input parent clock phandle for the clock. This should
0023 be a pll output.
0024 - #clock-cells : from common clock binding; shall be set to 0.
0025
0026
0027 Device Clocks
0028
0029 Device clocks are required to have one or both of the following sets of
0030 properties:
0031
0032
0033 Gated device clocks:
0034
0035 Required properties:
0036 - enable-reg : shall be the register offset from PMC base for the enable
0037 register.
0038 - enable-bit : shall be the bit within enable-reg to enable/disable the clock.
0039
0040
0041 Divisor device clocks:
0042
0043 Required property:
0044 - divisor-reg : shall be the register offset from PMC base for the divisor
0045 register.
0046 Optional property:
0047 - divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
0048 if not specified.
0049
0050
0051 For example:
0052
0053 ref25: ref25M {
0054 #clock-cells = <0>;
0055 compatible = "fixed-clock";
0056 clock-frequency = <25000000>;
0057 };
0058
0059 plla: plla {
0060 #clock-cells = <0>;
0061 compatible = "wm,wm8650-pll-clock";
0062 clocks = <&ref25>;
0063 reg = <0x200>;
0064 };
0065
0066 sdhc: sdhc {
0067 #clock-cells = <0>;
0068 compatible = "via,vt8500-device-clock";
0069 clocks = <&pllb>;
0070 divisor-reg = <0x328>;
0071 divisor-mask = <0x3f>;
0072 enable-reg = <0x254>;
0073 enable-bit = <18>;
0074 };
