bindings/clock/ti%2Clmk04832.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Clock bindings for the Texas Instruments LMK04832
0008
0009 maintainers:
0010   - Liam Beguin <liambeguin@gmail.com>
0011
0012 description: |
0013   Devicetree binding for the LMK04832, a clock conditioner with JEDEC JESD204B
0014   support. The LMK04832 is pin compatible with the LMK0482x family.
0015
0016   Link to datasheet, https://www.ti.com/lit/ds/symlink/lmk04832.pdf
0017
0018 properties:
0019   compatible:
0020     enum:
0021       - ti,lmk04832
0022
0023   reg:
0024     maxItems: 1
0025
0026   '#address-cells':
0027     const: 1
0028
0029   '#size-cells':
0030     const: 0
0031
0032   '#clock-cells':
0033     const: 1
0034
0035   spi-max-frequency:
0036     maximum: 5000000
0037
0038   clocks:
0039     items:
0040       - description: PLL2 reference clock.
0041
0042   clock-names:
0043     items:
0044       - const: oscin
0045
0046   reset-gpios:
0047     maxItems: 1
0048
0049   ti,spi-4wire-rdbk:
0050     description: |
0051       Select SPI 4wire readback pin configuration.
0052       Available readback pins are,
0053         CLKin_SEL0 0
0054         CLKin_SEL1 1
0055         RESET 2
0056     $ref: /schemas/types.yaml#/definitions/uint32
0057     enum: [0, 1, 2]
0058     default: 1
0059
0060   ti,vco-hz:
0061     description: Optional to set VCO frequency of the PLL in Hertz.
0062
0063   ti,sysref-ddly:
0064     description: SYSREF digital delay value.
0065     $ref: /schemas/types.yaml#/definitions/uint32
0066     minimum: 8
0067     maximum: 8191
0068     default: 8
0069
0070   ti,sysref-mux:
0071     description: |
0072       SYSREF Mux configuration.
0073       Available options are,
0074         Normal SYNC 0
0075         Re-clocked 1
0076         SYSREF Pulser 2
0077         SYSREF Continuous 3
0078     $ref: /schemas/types.yaml#/definitions/uint32
0079     enum: [0, 1, 2, 3]
0080     default: 3
0081
0082   ti,sync-mode:
0083     description: SYNC pin configuration.
0084     $ref: /schemas/types.yaml#/definitions/uint32
0085     enum: [0, 1, 2]
0086     default: 1
0087
0088   ti,sysref-pulse-count:
0089     description:
0090       Number of SYSREF pulses to send when SYSREF is not in continuous mode.
0091     $ref: /schemas/types.yaml#/definitions/uint32
0092     enum: [1, 2, 4, 8]
0093     default: 4
0094
0095 patternProperties:
0096   "@[0-9a-d]+$":
0097     type: object
0098     description:
0099       Child nodes used to configure output clocks.
0100
0101     properties:
0102       reg:
0103         description:
0104           clock output identifier.
0105         minimum: 0
0106         maximum: 13
0107
0108       ti,clkout-fmt:
0109         description:
0110           Clock output format.
0111           Available options are,
0112             Powerdown 0x00
0113             LVDS 0x01
0114             HSDS 6 mA 0x02
0115             HSDS 8 mA 0x03
0116             LVPECL 1600 mV 0x04
0117             LVPECL 2000 mV 0x05
0118             LCPECL 0x06
0119             CML 16 mA 0x07
0120             CML 24 mA 0x08
0121             CML 32 mA 0x09
0122             CMOS (Off/Inverted) 0x0a
0123             CMOS (Normal/Off) 0x0b
0124             CMOS (Inverted/Inverted) 0x0c
0125             CMOS (Inverted/Normal) 0x0d
0126             CMOS (Normal/Inverted) 0x0e
0127             CMOS (Normal/Normal) 0x0f
0128         $ref: /schemas/types.yaml#/definitions/uint32
0129         minimum: 0
0130         maximum: 15
0131
0132       ti,clkout-sysref:
0133         description:
0134           Select SYSREF clock path for output clock.
0135         type: boolean
0136
0137     required:
0138       - reg
0139
0140     additionalProperties: false
0141
0142 required:
0143   - compatible
0144   - reg
0145   - '#clock-cells'
0146   - clocks
0147   - clock-names
0148
0149 additionalProperties: false
0150
0151 examples:
0152   - |
0153     clocks {
0154         lmk04832_oscin: oscin {
0155             compatible = "fixed-clock";
0156
0157             #clock-cells = <0>;
0158             clock-frequency = <122880000>;
0159             clock-output-names = "lmk04832-oscin";
0160         };
0161     };
0162
0163     spi0 {
0164         #address-cells = <1>;
0165         #size-cells = <0>;
0166
0167         lmk04832: clock-controller@0 {
0168             #address-cells = <1>;
0169             #size-cells = <0>;
0170
0171             reg = <0>;
0172
0173             compatible = "ti,lmk04832";
0174             spi-max-frequency = <781250>;
0175
0176             reset-gpios = <&gpio_lmk 0 0 0>;
0177
0178             #clock-cells = <1>;
0179             clocks = <&lmk04832_oscin>;
0180             clock-names = "oscin";
0181
0182             ti,spi-4wire-rdbk = <0>;
0183             ti,vco-hz = <2457600000>;
0184
0185             assigned-clocks =
0186                 <&lmk04832 0>, <&lmk04832 1>,
0187                 <&lmk04832 2>, <&lmk04832 3>,
0188                 <&lmk04832 4>,
0189                 <&lmk04832 6>, <&lmk04832 7>,
0190                 <&lmk04832 10>, <&lmk04832 11>;
0191             assigned-clock-rates =
0192                 <122880000>, <384000>,
0193                 <122880000>, <384000>,
0194                 <122880000>,
0195                 <153600000>, <384000>,
0196                 <614400000>, <384000>;
0197
0198             clkout0@0 {
0199                 reg = <0>;
0200                 ti,clkout-fmt = <0x01>; // LVDS
0201             };
0202
0203             clkout1@1 {
0204                 reg = <1>;
0205                 ti,clkout-fmt = <0x01>; // LVDS
0206                 ti,clkout-sysref;
0207             };
0208         };
0209     };