Back to home page

OSCL-LXR

 
 

    


0001 Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.
0002 
0003 Reference
0004 This binding uses the common clock binding[1].
0005 
0006 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0007 [2] https://www.ti.com/product/cdce913
0008 [3] https://www.ti.com/product/cdce925
0009 [4] https://www.ti.com/product/cdce937
0010 [5] https://www.ti.com/product/cdce949
0011 
0012 The driver provides clock sources for each output Y1 through Y5.
0013 
0014 Required properties:
0015  - compatible: Shall be one of the following:
0016         - "ti,cdce913": 1-PLL, 3 Outputs
0017         - "ti,cdce925": 2-PLL, 5 Outputs
0018         - "ti,cdce937": 3-PLL, 7 Outputs
0019         - "ti,cdce949": 4-PLL, 9 Outputs
0020  - reg: I2C device address.
0021  - clocks: Points to a fixed parent clock that provides the input frequency.
0022  - #clock-cells: From common clock bindings: Shall be 1.
0023 
0024 Optional properties:
0025  - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
0026                  board, or to compensate for external influences.
0027 - vdd-supply: A regulator node for Vdd
0028 - vddout-supply: A regulator node for Vddout
0029 
0030 For all PLL1, PLL2, ... an optional child node can be used to specify spread
0031 spectrum clocking parameters for a board.
0032   - spread-spectrum: SSC mode as defined in the data sheet.
0033   - spread-spectrum-center: Use "centered" mode instead of "max" mode. When
0034     present, the clock runs at the requested frequency on average. Otherwise
0035     the requested frequency is the maximum value of the SCC range.
0036 
0037 
0038 Example:
0039 
0040         clockgen: cdce925pw@64 {
0041                 compatible = "cdce925";
0042                 reg = <0x64>;
0043                 clocks = <&xtal_27Mhz>;
0044                 #clock-cells = <1>;
0045                 xtal-load-pf = <5>;
0046                 vdd-supply = <&1v8-reg>;
0047                 vddout-supply = <&3v3-reg>;
0048                 /* PLL options to get SSC 1% centered */
0049                 PLL2 {
0050                         spread-spectrum = <4>;
0051                         spread-spectrum-center;
0052                 };
0053         };