0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ST-Ericsson DB8500 (U8500) clocks
0008
0009 maintainers:
0010 - Ulf Hansson <ulf.hansson@linaro.org>
0011 - Linus Walleij <linus.walleij@linaro.org>
0012
0013 description: While named "U8500 clocks" these clocks are inside the
0014 DB8500 digital baseband system-on-chip and its siblings such as
0015 DB8520. These bindings consider the clocks present in the SoC
0016 itself, not off-chip clocks. There are four different on-chip
0017 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
0018 control management unit) clocks and PRCC (peripheral reset and
0019 clock controller) clocks. For some reason PRCC 4 does not exist so
0020 the itemization can be a bit unintuitive.
0021
0022 properties:
0023 compatible:
0024 enum:
0025 - stericsson,u8500-clks
0026 - stericsson,u8540-clks
0027 - stericsson,u9540-clks
0028
0029 reg:
0030 items:
0031 - description: PRCC 1 register area
0032 - description: PRCC 2 register area
0033 - description: PRCC 3 register area
0034 - description: PRCC 5 register area
0035 - description: PRCC 6 register area
0036
0037 prcmu-clock:
0038 description: A subnode with one clock cell for PRCMU (power, reset, control
0039 management unit) clocks. The cell indicates which PRCMU clock in the
0040 prcmu-clock node the consumer wants to use.
0041 type: object
0042
0043 properties:
0044 '#clock-cells':
0045 const: 1
0046
0047 additionalProperties: false
0048
0049 prcc-periph-clock:
0050 description: A subnode with two clock cells for PRCC (peripheral
0051 reset and clock controller) peripheral clocks. The first cell indicates
0052 which PRCC block the consumer wants to use, possible values are 1, 2, 3,
0053 5, 6. The second cell indicates which clock inside the PRCC block it
0054 wants, possible values are 0 thru 31.
0055 type: object
0056
0057 properties:
0058 '#clock-cells':
0059 const: 2
0060
0061 additionalProperties: false
0062
0063 prcc-kernel-clock:
0064 description: A subnode with two clock cells for PRCC (peripheral reset
0065 and clock controller) kernel clocks. The first cell indicates which PRCC
0066 block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The
0067 second cell indicates which clock inside the PRCC block it wants, possible
0068 values are 0 thru 31.
0069 type: object
0070
0071 properties:
0072 '#clock-cells':
0073 const: 2
0074
0075 additionalProperties: false
0076
0077 prcc-reset-controller:
0078 description: A subnode with two reset cells for the reset portions of the
0079 PRCC (peripheral reset and clock controller). The first cell indicates
0080 which PRCC block the consumer wants to use, possible values are 1, 2, 3
0081 5 and 6. The second cell indicates which reset line inside the PRCC block
0082 it wants to control, possible values are 0 thru 31.
0083 type: object
0084
0085 properties:
0086 '#reset-cells':
0087 const: 2
0088
0089 additionalProperties: false
0090
0091 rtc32k-clock:
0092 description: A subnode with zero clock cells for the 32kHz RTC clock.
0093 type: object
0094
0095 properties:
0096 '#clock-cells':
0097 const: 0
0098
0099 additionalProperties: false
0100
0101 smp-twd-clock:
0102 description: A subnode for the ARM SMP Timer Watchdog cluster with zero
0103 clock cells.
0104 type: object
0105
0106 properties:
0107 '#clock-cells':
0108 const: 0
0109
0110 additionalProperties: false
0111
0112 clkout-clock:
0113 description: A subnode with three clock cells for externally routed clocks,
0114 output clocks. These are two PRCMU-internal clocks that can be divided and
0115 muxed out on the pads of the DB8500 SoC.
0116 type: object
0117
0118 properties:
0119 '#clock-cells':
0120 description:
0121 The first cell indicates which output clock we are using,
0122 possible values are 0 (CLKOUT1) and 1 (CLKOUT2).
0123 The second cell indicates which clock we want to use as source,
0124 possible values are 0 thru 7, see the defines for the different
0125 source clocks.
0126 The third cell is a divider, legal values are 1 thru 63.
0127 const: 3
0128
0129 additionalProperties: false
0130
0131 required:
0132 - compatible
0133 - reg
0134 - prcmu-clock
0135 - prcc-periph-clock
0136 - prcc-kernel-clock
0137 - rtc32k-clock
0138 - smp-twd-clock
0139
0140 additionalProperties: false
0141
0142 examples:
0143 - |
0144 #include <dt-bindings/clock/ste-db8500-clkout.h>
0145 clocks@8012 {
0146 compatible = "stericsson,u8500-clks";
0147 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
0148 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
0149 <0xa03cf000 0x1000>;
0150
0151 prcmu_clk: prcmu-clock {
0152 #clock-cells = <1>;
0153 };
0154
0155 prcc_pclk: prcc-periph-clock {
0156 #clock-cells = <2>;
0157 };
0158
0159 prcc_kclk: prcc-kernel-clock {
0160 #clock-cells = <2>;
0161 };
0162
0163 prcc_reset: prcc-reset-controller {
0164 #reset-cells = <2>;
0165 };
0166
0167 rtc_clk: rtc32k-clock {
0168 #clock-cells = <0>;
0169 };
0170
0171 smp_twd_clk: smp-twd-clock {
0172 #clock-cells = <0>;
0173 };
0174
0175 clkout_clk: clkout-clock {
0176 #clock-cells = <3>;
0177 };
0178 };
