0001 Binding for a type of quad channel digital frequency synthesizer found on
0002 certain STMicroelectronics consumer electronics SoC devices.
0003
0004 This version contains a programmable PLL which can generate up to 216, 432
0005 or 660MHz (from a 30MHz oscillator input) as the input to the digital
0006 synthesizers.
0007
0008 This binding uses the common clock binding[1].
0009
0010 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0011
0012 Required properties:
0013 - compatible : shall be:
0014 "st,quadfs"
0015 "st,quadfs-d0"
0016 "st,quadfs-d2"
0017 "st,quadfs-d3"
0018 "st,quadfs-pll"
0019
0020
0021 - #clock-cells : from common clock binding; shall be set to 1.
0022
0023 - reg : A Base address and length of the register set.
0024
0025 - clocks : from common clock binding
0026
0027 - clock-output-names : From common clock binding. The block has 4
0028 clock outputs but not all of them in a specific instance
0029 have to be used in the SoC. If a clock name is left as
0030 an empty string then no clock will be created for the
0031 output associated with that string index. If fewer than
0032 4 strings are provided then no clocks will be created
0033 for the remaining outputs.
0034
0035 Example:
0036
0037 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
0038 #clock-cells = <1>;
0039 compatible = "st,quadfs-pll";
0040 reg = <0x9103000 0x1000>;
0041
0042 clocks = <&clk_sysin>;
0043
0044 clock-output-names = "clk-s-c0-fs0-ch0",
0045 "clk-s-c0-fs0-ch1",
0046 "clk-s-c0-fs0-ch2",
0047 "clk-s-c0-fs0-ch3";
0048 };
