0001 Binding for a type of flexgen structure found on certain
0002 STMicroelectronics consumer electronics SoC devices
0003
0004 This structure includes:
0005 - a clock cross bar (represented by a mux element)
0006 - a pre and final dividers (represented by a divider and gate elements)
0007
0008 Flexgen structure is a part of Clockgen[1].
0009
0010 Please find an example below:
0011
0012 Clockgen block diagram
0013 -------------------------------------------------------------------
0014 | Flexgen structure |
0015 | --------------------------------------------- |
0016 | | ------- -------- -------- | |
0017 clk_sysin | | | | | | | | |
0018 ---|-----------------|-->| | | | | | | |
0019 | | | | | | | | | | |
0020 | | ------- | | | |Pre | |Final | | |
0021 | | |PLL0 | | | | |Dividers| |Dividers| | |
0022 | |->| | | | | | x32 | | x32 | | |
0023 | | | odf_0|----|-->| | | | | | | |
0024 | | | | | | | | | | | | |
0025 | | | | | | | | | | | | |
0026 | | | | | | | | | | | | |
0027 | | | | | | | | | | | | |
0028 | | ------- | | | | | | | | |
0029 | | | | | | | | | | |
0030 | | ------- | | Clock | | | | | | |
0031 | | |PLL1 | | | | | | | | | |
0032 | |->| | | | Cross | | | | | | |
0033 | | | odf_0|----|-->| | | | | | CLK_DIV[31:0]
0034 | | | | | | Bar |====>| |====>| |===|=========>
0035 | | | | | | | | | | | | |
0036 | | | | | | | | | | | | |
0037 | | | | | | | | | | | | |
0038 | | ------- | | | | | | | | |
0039 | | | | | | | | | | |
0040 | | ------- | | | | | | | | |
0041 | | |QUADFS | | | | | | | | | |
0042 | |->| ch0|----|-->| | | | | | | |
0043 | | | | | | | | | | | |
0044 | | ch1|----|-->| | | | | | | |
0045 | | | | | | | | | | | |
0046 | | ch2|----|-->| | | DIV | | DIV | | |
0047 | | | | | | | 1 to | | 1 to | | |
0048 | | ch3|----|-->| | | 1024 | | 64 | | |
0049 | ------- | | | | | | | | |
0050 | | ------- -------- -------- | |
0051 | -------------------------------------------- |
0052 | |
0053 -------------------------------------------------------------------
0054
0055 This binding uses the common clock binding[2].
0056
0057 [1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
0058 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
0059
0060 Required properties:
0061 - compatible : shall be:
0062 "st,flexgen"
0063 "st,flexgen-audio", "st,flexgen" (enable clock propagation on parent for
0064 audio use case)
0065 "st,flexgen-video", "st,flexgen" (enable clock propagation on parent
0066 and activate synchronous mode)
0067 "st,flexgen-stih407-a0"
0068 "st,flexgen-stih410-a0"
0069 "st,flexgen-stih407-c0"
0070 "st,flexgen-stih410-c0"
0071 "st,flexgen-stih418-c0"
0072 "st,flexgen-stih407-d0"
0073 "st,flexgen-stih410-d0"
0074 "st,flexgen-stih407-d2"
0075 "st,flexgen-stih418-d2"
0076 "st,flexgen-stih407-d3"
0077
0078 - #clock-cells : from common clock binding; shall be set to 1 (multiple clock
0079 outputs).
0080
0081 - clocks : must be set to the parent's phandle. it could be output clocks of
0082 a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
0083
0084 - clock-output-names : List of strings used to name the clock outputs.
0085
0086 Example:
0087
0088 clk_s_c0_flexgen: clk-s-c0-flexgen {
0089
0090 #clock-cells = <1>;
0091 compatible = "st,flexgen";
0092
0093 clocks = <&clk_s_c0_pll0 0>,
0094 <&clk_s_c0_pll1 0>,
0095 <&clk_s_c0_quadfs 0>,
0096 <&clk_s_c0_quadfs 1>,
0097 <&clk_s_c0_quadfs 2>,
0098 <&clk_s_c0_quadfs 3>,
0099 <&clk_sysin>;
0100
0101 clock-output-names = "clk-icn-gpu",
0102 "clk-fdma",
0103 "clk-nand",
0104 "clk-hva",
0105 "clk-proc-stfe",
0106 "clk-proc-tp",
0107 "clk-rx-icn-dmu",
0108 "clk-rx-icn-hva",
0109 "clk-icn-cpu",
0110 "clk-tx-icn-dmu",
0111 "clk-mmc-0",
0112 "clk-mmc-1",
0113 "clk-jpegdec",
0114 "clk-ext2fa9",
0115 "clk-ic-bdisp-0",
0116 "clk-ic-bdisp-1",
0117 "clk-pp-dmu",
0118 "clk-vid-dmu",
0119 "clk-dss-lpc",
0120 "clk-st231-aud-0",
0121 "clk-st231-gp-1",
0122 "clk-st231-dmu",
0123 "clk-icn-lmi",
0124 "clk-tx-icn-disp-1",
0125 "clk-icn-sbc",
0126 "clk-stfe-frc2",
0127 "clk-eth-phy",
0128 "clk-eth-ref-phyclk",
0129 "clk-flash-promip",
0130 "clk-main-disp",
0131 "clk-aux-disp",
0132 "clk-compo-dvp";
0133 };
