0001 Binding for a Clockgen hardware block found on
0002 certain STMicroelectronics consumer electronics SoC devices.
0003
0004 A Clockgen node can contain pll, diviser or multiplexer nodes.
0005
0006 We will find only the base address of the Clockgen, this base
0007 address is common of all subnode.
0008
0009 clockgen_node {
0010 reg = <>;
0011
0012 pll_node {
0013 ...
0014 };
0015
0016 quadfs_node {
0017 ...
0018 };
0019
0020 mux_node {
0021 ...
0022 };
0023
0024 flexgen_node {
0025 ...
0026 };
0027 ...
0028 };
0029
0030 This binding uses the common clock binding[1].
0031 Each subnode should use the binding described in [2]..[7]
0032
0033 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0034 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
0035 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
0036 [7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt
0037 [8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt
0038
0039
0040 Required properties:
0041 - reg : A Base address and length of the register set.
0042
0043 Example:
0044
0045 clockgen-a@90ff000 {
0046 compatible = "st,clkgen-c32";
0047 reg = <0x90ff000 0x1000>;
0048
0049 clk_s_a0_pll: clk-s-a0-pll {
0050 #clock-cells = <1>;
0051 compatible = "st,clkgen-pll0";
0052
0053 clocks = <&clk_sysin>;
0054
0055 clock-output-names = "clk-s-a0-pll-ofd-0";
0056 };
0057
0058 clk_s_a0_flexgen: clk-s-a0-flexgen {
0059 compatible = "st,flexgen";
0060
0061 #clock-cells = <1>;
0062
0063 clocks = <&clk_s_a0_pll 0>,
0064 <&clk_sysin>;
0065
0066 clock-output-names = "clk-ic-lmi0";
0067 };
0068 };
