clock/st/st%2Cclkgen-pll.txt

0001 Binding for a ST pll clock driver.
0002
0003 This binding uses the common clock binding[1].
0004 Base address is located to the parent node. See clock binding[2]
0005
0006 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0007 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
0008
0009 Required properties:
0010
0011 - compatible : shall be:
0012         "st,clkgen-pll0"
0013         "st,clkgen-pll0-a0"
0014         "st,clkgen-pll0-c0"
0015         "st,clkgen-pll1"
0016         "st,clkgen-pll1-c0"
0017         "st,stih407-clkgen-plla9"
0018         "st,stih418-clkgen-plla9"
0019
0020 - #clock-cells : From common clock binding; shall be set to 1.
0021
0022 - clocks : From common clock binding
0023
0024 - clock-output-names : From common clock binding.
0025
0026 Example:
0027
0028         clockgen-a9@92b0000 {
0029                 compatible = "st,clkgen-c32";
0030                 reg = <0x92b0000 0xffff>;
0031
0032                 clockgen_a9_pll: clockgen-a9-pll {
0033                         #clock-cells = <1>;
0034                         compatible = "st,stih407-clkgen-plla9";
0035
0036                         clocks = <&clk_sysin>;
0037
0038                         clock-output-names = "clockgen-a9-pll-odf";
0039                 };
0040         };