0001 STMicroelectronics STM32H7 Reset and Clock Controller
0002 =====================================================
0003
0004 The RCC IP is both a reset and a clock controller.
0005
0006 Please refer to clock-bindings.txt for common clock controller binding usage.
0007 Please also refer to reset.txt for common reset controller binding usage.
0008
0009 Required properties:
0010 - compatible: Should be:
0011 "st,stm32h743-rcc"
0012
0013 - reg: should be register base and length as documented in the
0014 datasheet
0015
0016 - #reset-cells: 1, see below
0017
0018 - #clock-cells : from common clock binding; shall be set to 1
0019
0020 - clocks: External oscillator clock phandle
0021 - high speed external clock signal (HSE)
0022 - low speed external clock signal (LSE)
0023 - external I2S clock (I2S_CKIN)
0024
0025 Optional properties:
0026 - st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
0027 write protection (RTC clock).
0028
0029 Example:
0030
0031 rcc: reset-clock-controller@58024400 {
0032 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
0033 reg = <0x58024400 0x400>;
0034 #reset-cells = <1>;
0035 #clock-cells = <1>;
0036 clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
0037
0038 st,syscfg = <&pwrcfg>;
0039 };
0040
0041 The peripheral clock consumer should specify the desired clock by
0042 having the clock ID in its "clocks" phandle cell.
0043
0044 Example:
0045
0046 timer5: timer@40000c00 {
0047 compatible = "st,stm32-timer";
0048 reg = <0x40000c00 0x400>;
0049 interrupts = <50>;
0050 clocks = <&rcc TIM5_CK>;
0051 };
0052
0053 Specifying softreset control of devices
0054 =======================================
0055
0056 Device nodes should specify the reset channel required in their "resets"
0057 property, containing a phandle to the reset device node and an index specifying
0058 which channel to use.
0059 The index is the bit number within the RCC registers bank, starting from RCC
0060 base address.
0061 It is calculated as: index = register_offset / 4 * 32 + bit_offset.
0062 Where bit_offset is the bit offset within the register.
0063
0064 For example, for CRC reset:
0065 crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
0066
0067 Example:
0068
0069 timer2 {
0070 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
0071 };
