0001 STMicroelectronics STM32 Reset and Clock Controller
0002 ===================================================
0003
0004 The RCC IP is both a reset and a clock controller.
0005
0006 Please refer to clock-bindings.txt for common clock controller binding usage.
0007 Please also refer to reset.txt for common reset controller binding usage.
0008
0009 Required properties:
0010 - compatible: Should be:
0011 "st,stm32f42xx-rcc"
0012 "st,stm32f469-rcc"
0013 "st,stm32f746-rcc"
0014 "st,stm32f769-rcc"
0015
0016 - reg: should be register base and length as documented in the
0017 datasheet
0018 - #reset-cells: 1, see below
0019 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
0020 property, containing a phandle to the clock device node, an index selecting
0021 between gated clocks and other clocks and an index specifying the clock to
0022 use.
0023 - clocks: External oscillator clock phandle
0024 - high speed external clock signal (HSE)
0025 - external I2S clock (I2S_CKIN)
0026
0027 Example:
0028
0029 rcc: rcc@40023800 {
0030 #reset-cells = <1>;
0031 #clock-cells = <2>
0032 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
0033 reg = <0x40023800 0x400>;
0034 clocks = <&clk_hse>, <&clk_i2s_ckin>;
0035 };
0036
0037 Specifying gated clocks
0038 =======================
0039
0040 The primary index must be set to 0.
0041
0042 The secondary index is the bit number within the RCC register bank, starting
0043 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
0044
0045 It is calculated as: index = register_offset / 4 * 32 + bit_offset.
0046 Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
0047
0048 To simplify the usage and to share bit definition with the reset and clock
0049 drivers of the RCC IP, macros are available to generate the index in
0050 human-readble format.
0051
0052 For STM32F4 series, the macro are available here:
0053 - include/dt-bindings/mfd/stm32f4-rcc.h
0054
0055 Example:
0056
0057 /* Gated clock, AHB1 bit 0 (GPIOA) */
0058 ... {
0059 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
0060 };
0061
0062 /* Gated clock, AHB2 bit 4 (CRYP) */
0063 ... {
0064 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
0065 };
0066
0067 Specifying other clocks
0068 =======================
0069
0070 The primary index must be set to 1.
0071
0072 The secondary index is bound with the following magic numbers:
0073
0074 0 SYSTICK
0075 1 FCLK
0076 2 CLK_LSI (low-power clock source)
0077 3 CLK_LSE (generated from a 32.768 kHz low-speed external
0078 crystal or ceramic resonator)
0079 4 CLK_HSE_RTC (HSE division factor for RTC clock)
0080 5 CLK_RTC (real-time clock)
0081 6 PLL_VCO_I2S (vco frequency of I2S pll)
0082 7 PLL_VCO_SAI (vco frequency of SAI pll)
0083 8 CLK_LCD (LCD-TFT)
0084 9 CLK_I2S (I2S clocks)
0085 10 CLK_SAI1 (audio clocks)
0086 11 CLK_SAI2
0087 12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor)
0088 13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor)
0089
0090 14 CLK_HSI (Internal ocscillator clock)
0091 15 CLK_SYSCLK (System Clock)
0092 16 CLK_HDMI_CEC (HDMI-CEC clock)
0093 17 CLK_SPDIF (SPDIF-Rx clock)
0094 18 CLK_USART1 (U(s)arts clocks)
0095 19 CLK_USART2
0096 20 CLK_USART3
0097 21 CLK_UART4
0098 22 CLK_UART5
0099 23 CLK_USART6
0100 24 CLK_UART7
0101 25 CLK_UART8
0102 26 CLK_I2C1 (I2S clocks)
0103 27 CLK_I2C2
0104 28 CLK_I2C3
0105 29 CLK_I2C4
0106 30 CLK_LPTIMER (LPTimer1 clock)
0107 31 CLK_PLL_SRC
0108 32 CLK_DFSDM1
0109 33 CLK_ADFSDM1
0110 34 CLK_F769_DSI
0111 )
0112
0113 Example:
0114
0115 /* Misc clock, FCLK */
0116 ... {
0117 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
0118 };
0119
0120
0121 Specifying softreset control of devices
0122 =======================================
0123
0124 Device nodes should specify the reset channel required in their "resets"
0125 property, containing a phandle to the reset device node and an index specifying
0126 which channel to use.
0127 The index is the bit number within the RCC registers bank, starting from RCC
0128 base address.
0129 It is calculated as: index = register_offset / 4 * 32 + bit_offset.
0130 Where bit_offset is the bit offset within the register.
0131 For example, for CRC reset:
0132 crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
0133
0134 example:
0135
0136 timer2 {
0137 resets = <&rcc STM32F4_APB1_RESET(TIM2)>;
0138 };
