0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright 2022 Unisoc Inc.
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: UMS512 Soc clock controller
0009
0010 maintainers:
0011 - Orson Zhai <orsonzhai@gmail.com>
0012 - Baolin Wang <baolin.wang7@gmail.com>
0013 - Chunyan Zhang <zhang.lyra@gmail.com>
0014
0015 properties:
0016 compatible:
0017 enum:
0018 - sprd,ums512-apahb-gate
0019 - sprd,ums512-ap-clk
0020 - sprd,ums512-aonapb-clk
0021 - sprd,ums512-pmu-gate
0022 - sprd,ums512-g0-pll
0023 - sprd,ums512-g2-pll
0024 - sprd,ums512-g3-pll
0025 - sprd,ums512-gc-pll
0026 - sprd,ums512-aon-gate
0027 - sprd,ums512-audcpapb-gate
0028 - sprd,ums512-audcpahb-gate
0029 - sprd,ums512-gpu-clk
0030 - sprd,ums512-mm-clk
0031 - sprd,ums512-mm-gate-clk
0032 - sprd,ums512-apapb-gate
0033
0034 "#clock-cells":
0035 const: 1
0036
0037 clocks:
0038 minItems: 1
0039 maxItems: 4
0040 description: |
0041 The input parent clock(s) phandle for the clock, only list
0042 fixed clocks which are declared in devicetree.
0043
0044 clock-names:
0045 minItems: 1
0046 items:
0047 - const: ext-26m
0048 - const: ext-32k
0049 - const: ext-4m
0050 - const: rco-100m
0051
0052 reg:
0053 maxItems: 1
0054
0055 required:
0056 - compatible
0057 - '#clock-cells'
0058 - reg
0059
0060 additionalProperties: false
0061
0062 examples:
0063 - |
0064 ap_clk: clock-controller@20200000 {
0065 compatible = "sprd,ums512-ap-clk";
0066 reg = <0x20200000 0x1000>;
0067 clocks = <&ext_26m>;
0068 clock-names = "ext-26m";
0069 #clock-cells = <1>;
0070 };
0071 ...
