0001 Binding for the AXS10X Generic PLL clock
0002
0003 This binding uses the common clock binding[1].
0004
0005 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0006
0007 Required properties:
0008 - compatible: should be "snps,axs10x-<name>-pll-clock"
0009 "snps,axs10x-arc-pll-clock"
0010 "snps,axs10x-pgu-pll-clock"
0011 - reg: should always contain 2 pairs address - length: first for PLL config
0012 registers and second for corresponding LOCK CGU register.
0013 - clocks: shall be the input parent clock phandle for the PLL.
0014 - #clock-cells: from common clock binding; Should always be set to 0.
0015
0016 Example:
0017 input-clk: input-clk {
0018 clock-frequency = <33333333>;
0019 compatible = "fixed-clock";
0020 #clock-cells = <0>;
0021 };
0022
0023 core-clk: core-clk@80 {
0024 compatible = "snps,axs10x-arc-pll-clock";
0025 reg = <0x80 0x10>, <0x100 0x10>;
0026 #clock-cells = <0>;
0027 clocks = <&input-clk>;
0028 };
