0001 Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
0002
0003 Reference
0004 [1] Si5351A/B/C Data Sheet
0005 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
0006
0007 The Si5351a/b/c are programmable i2c clock generators with up to 8 output
0008 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
0009 3 output clocks are accessible. The internal structure of the clock
0010 generators can be found in [1].
0011
0012 ==I2C device node==
0013
0014 Required properties:
0015 - compatible: shall be one of the following:
0016 "silabs,si5351a" - Si5351a, QFN20 package
0017 "silabs,si5351a-msop" - Si5351a, MSOP10 package
0018 "silabs,si5351b" - Si5351b, QFN20 package
0019 "silabs,si5351c" - Si5351c, QFN20 package
0020 - reg: i2c device address, shall be 0x60 or 0x61.
0021 - #clock-cells: from common clock binding; shall be set to 1.
0022 - clocks: from common clock binding; list of parent clock
0023 handles, shall be xtal reference clock or xtal and clkin for
0024 si5351c only. Corresponding clock input names are "xtal" and
0025 "clkin" respectively.
0026 - #address-cells: shall be set to 1.
0027 - #size-cells: shall be set to 0.
0028
0029 Optional properties:
0030 - silabs,pll-source: pair of (number, source) for each pll. Allows
0031 to overwrite clock source of pll A (number=0) or B (number=1).
0032
0033 ==Child nodes==
0034
0035 Each of the clock outputs can be overwritten individually by
0036 using a child node to the I2C device node. If a child node for a clock
0037 output is not set, the eeprom configuration is not overwritten.
0038
0039 Required child node properties:
0040 - reg: number of clock output.
0041
0042 Optional child node properties:
0043 - silabs,clock-source: source clock of the output divider stage N, shall be
0044 0 = multisynth N
0045 1 = multisynth 0 for output clocks 0-3, else multisynth4
0046 2 = xtal
0047 3 = clkin (si5351c only)
0048 - silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
0049 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
0050 divider.
0051 - silabs,pll-master: boolean, multisynth can change pll frequency.
0052 - silabs,pll-reset: boolean, clock output can reset its pll.
0053 - silabs,disable-state : clock output disable state, shall be
0054 0 = clock output is driven LOW when disabled
0055 1 = clock output is driven HIGH when disabled
0056 2 = clock output is FLOATING (HIGH-Z) when disabled
0057 3 = clock output is NEVER disabled
0058
0059 ==Example==
0060
0061 /* 25MHz reference crystal */
0062 ref25: ref25M {
0063 compatible = "fixed-clock";
0064 #clock-cells = <0>;
0065 clock-frequency = <25000000>;
0066 };
0067
0068 i2c-master-node {
0069
0070 /* Si5351a msop10 i2c clock generator */
0071 si5351a: clock-generator@60 {
0072 compatible = "silabs,si5351a-msop";
0073 reg = <0x60>;
0074 #address-cells = <1>;
0075 #size-cells = <0>;
0076 #clock-cells = <1>;
0077
0078 /* connect xtal input to 25MHz reference */
0079 clocks = <&ref25>;
0080 clock-names = "xtal";
0081
0082 /* connect xtal input as source of pll0 and pll1 */
0083 silabs,pll-source = <0 0>, <1 0>;
0084
0085 /*
0086 * overwrite clkout0 configuration with:
0087 * - 8mA output drive strength
0088 * - pll0 as clock source of multisynth0
0089 * - multisynth0 as clock source of output divider
0090 * - multisynth0 can change pll0
0091 * - set initial clock frequency of 74.25MHz
0092 */
0093 clkout0 {
0094 reg = <0>;
0095 silabs,drive-strength = <8>;
0096 silabs,multisynth-source = <0>;
0097 silabs,clock-source = <0>;
0098 silabs,pll-master;
0099 clock-frequency = <74250000>;
0100 };
0101
0102 /*
0103 * overwrite clkout1 configuration with:
0104 * - 4mA output drive strength
0105 * - pll1 as clock source of multisynth1
0106 * - multisynth1 as clock source of output divider
0107 * - multisynth1 can change pll1
0108 */
0109 clkout1 {
0110 reg = <1>;
0111 silabs,drive-strength = <4>;
0112 silabs,multisynth-source = <1>;
0113 silabs,clock-source = <0>;
0114 pll-master;
0115 };
0116
0117 /*
0118 * overwrite clkout2 configuration with:
0119 * - xtal as clock source of output divider
0120 */
0121 clkout2 {
0122 reg = <2>;
0123 silabs,clock-source = <2>;
0124 };
0125 };
0126 };
