0001 Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable
0002 i2c clock generator.
0003
0004 Reference
0005 [1] Si5341 Data Sheet
0006 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
0007 [2] Si5341 Reference Manual
0008 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
0009 [3] Si5345 Reference Manual
0010 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
0011
0012 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
0013 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
0014 in turn can be directed to any of the 10 (or 4) outputs through a divider.
0015 The internal structure of the clock generators can be found in [2].
0016 The Si5345 is similar to the Si5341 with the addition of fractional input
0017 dividers and automatic input selection, as described in [3].
0018 The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
0019
0020 The driver can be used in "as is" mode, reading the current settings from the
0021 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
0022 configured when the driver probes, it assumes the driver must fully initialize
0023 it.
0024
0025 The device type, speed grade and revision are determined runtime by probing.
0026
0027 The driver currently does not support any fancy input configurations. They can
0028 still be programmed into the chip and the driver will leave them "as is".
0029
0030 ==I2C device node==
0031
0032 Required properties:
0033 - compatible: shall be one of the following:
0034 "silabs,si5340" - Si5340 A/B/C/D
0035 "silabs,si5341" - Si5341 A/B/C/D
0036 "silabs,si5342" - Si5342 A/B/C/D
0037 "silabs,si5344" - Si5344 A/B/C/D
0038 "silabs,si5345" - Si5345 A/B/C/D
0039 - reg: i2c device address, usually 0x74
0040 - #clock-cells: from common clock binding; shall be set to 2.
0041 The first value is "0" for outputs, "1" for synthesizers.
0042 The second value is the output or synthesizer index.
0043 - clocks: from common clock binding; list of parent clock handles,
0044 corresponding to inputs. Use a fixed clock for the "xtal" input.
0045 At least one must be present.
0046 - clock-names: One of: "xtal", "in0", "in1", "in2"
0047
0048 Optional properties:
0049 - vdd-supply: Regulator node for VDD
0050 - vdda-supply: Regulator node for VDDA
0051 - vdds-supply: Regulator node for VDDS
0052 - silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
0053 feedback divider. Must be such that the PLL output is in the valid range. For
0054 example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
0055 the fraction matters, using 3500 and 12 will deliver the exact same result.
0056 If these are not specified, and the PLL is not yet programmed when the driver
0057 probes, the PLL will be set to 14GHz.
0058 - silabs,reprogram: When present, the driver will always assume the device must
0059 be initialized, and always performs the soft-reset routine. Since this will
0060 temporarily stop all output clocks, don't do this if the chip is generating
0061 the CPU clock for example.
0062 - silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
0063 in EXTCLK (external reference clock) rather than XTAL (crystal) mode.
0064 - interrupts: Interrupt for INTRb pin.
0065 - silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V
0066 rather than 1.8V thresholds.
0067 - vddoX-supply (where X is an output index): Regulator node for VDDO for the
0068 specified output. The driver selects the output VDD_SEL setting based on this
0069 voltage.
0070 - #address-cells: shall be set to 1.
0071 - #size-cells: shall be set to 0.
0072
0073
0074 == Child nodes: Outputs ==
0075
0076 The child nodes list the output clocks.
0077
0078 Each of the clock outputs can be overwritten individually by using a child node.
0079 If a child node for a clock output is not set, the configuration remains
0080 unchanged.
0081
0082 Required child node properties:
0083 - reg: number of clock output.
0084
0085 Optional child node properties:
0086 - silabs,format: Output format, one of:
0087 1 = differential (defaults to LVDS levels)
0088 2 = low-power (defaults to HCSL levels)
0089 4 = LVCMOS
0090 - silabs,common-mode: Manually override output common mode, see [2] for values
0091 - silabs,amplitude: Manually override output amplitude, see [2] for values
0092 - silabs,synth-master: boolean. If present, this output is allowed to change the
0093 multisynth frequency dynamically.
0094 - silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
0095 when disabled, otherwise it's driven LOW.
0096
0097 ==Example==
0098
0099 /* 48MHz reference crystal */
0100 ref48: ref48M {
0101 compatible = "fixed-clock";
0102 #clock-cells = <0>;
0103 clock-frequency = <48000000>;
0104 };
0105
0106 i2c-master-node {
0107 /* Programmable clock (for logic) */
0108 si5341: clock-generator@74 {
0109 reg = <0x74>;
0110 compatible = "silabs,si5341";
0111 #clock-cells = <2>;
0112 #address-cells = <1>;
0113 #size-cells = <0>;
0114 clocks = <&ref48>;
0115 clock-names = "xtal";
0116
0117 silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
0118 silabs,pll-m-den = <48>;
0119 silabs,reprogram; /* Chips are not programmed, always reset */
0120
0121 out@0 {
0122 reg = <0>;
0123 silabs,format = <1>; /* LVDS 3v3 */
0124 silabs,common-mode = <3>;
0125 silabs,amplitude = <3>;
0126 silabs,synth-master;
0127 };
0128
0129 /*
0130 * Output 6 configuration:
0131 * LVDS 1v8
0132 */
0133 out@6 {
0134 reg = <6>;
0135 silabs,format = <1>; /* LVDS 1v8 */
0136 silabs,common-mode = <13>;
0137 silabs,amplitude = <3>;
0138 };
0139
0140 /*
0141 * Output 8 configuration:
0142 * HCSL 3v3
0143 */
0144 out@8 {
0145 reg = <8>;
0146 silabs,format = <2>;
0147 silabs,common-mode = <11>;
0148 silabs,amplitude = <3>;
0149 };
0150 };
0151 };
0152
0153 some-video-node {
0154 /* Standard clock bindings */
0155 clock-names = "pixel";
0156 clocks = <&si5341 0 7>; /* Output 7 */
0157
0158 /* Set output 7 to use syntesizer 3 as its parent */
0159 assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
0160 assigned-clock-parents = <&si5341 1 3>;
0161 /* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
0162 assigned-clock-rates = <148500000>, <594000000>;
0163 };
0164
0165 some-audio-node {
0166 clock-names = "i2s-clk";
0167 clocks = <&si5341 0 0>;
0168 /*
0169 * since output 0 is a synth-master, the synth will be automatically set
0170 * to an appropriate frequency when the audio driver requests another
0171 * frequency. We give control over synth 2 to this output here.
0172 */
0173 assigned-clocks = <&si5341 0 0>;
0174 assigned-clock-parents = <&si5341 1 2>;
0175 };
