0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2020 SiFive, Inc.
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
0009
0010 maintainers:
0011 - Sagar Kadam <sagar.kadam@sifive.com>
0012 - Paul Walmsley <paul.walmsley@sifive.com>
0013
0014 description:
0015 On the FU540 family of SoCs, most system-wide clock and reset integration
0016 is via the PRCI IP block.
0017 The clock consumer should specify the desired clock via the clock ID
0018 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
0019 These macros begin with PRCI_CLK_.
0020
0021 The hfclk and rtcclk nodes are required, and represent physical
0022 crystals or resonators located on the PCB. These nodes should be present
0023 underneath /, rather than /soc.
0024
0025 properties:
0026 compatible:
0027 const: sifive,fu540-c000-prci
0028
0029 reg:
0030 maxItems: 1
0031
0032 clocks:
0033 items:
0034 - description: high frequency clock.
0035 - description: RTL clock.
0036
0037 clock-names:
0038 items:
0039 - const: hfclk
0040 - const: rtcclk
0041
0042 "#clock-cells":
0043 const: 1
0044
0045 required:
0046 - compatible
0047 - reg
0048 - clocks
0049 - "#clock-cells"
0050
0051 additionalProperties: false
0052
0053 examples:
0054 - |
0055 prci: clock-controller@10000000 {
0056 compatible = "sifive,fu540-c000-prci";
0057 reg = <0x10000000 0x1000>;
0058 clocks = <&hfclk>, <&rtcclk>;
0059 #clock-cells = <1>;
0060 };
