0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung Exynos7 SoC clock controller
0008
0009 maintainers:
0010 - Chanwoo Choi <cw00.choi@samsung.com>
0011 - Krzysztof Kozlowski <krzk@kernel.org>
0012 - Sylwester Nawrocki <s.nawrocki@samsung.com>
0013 - Tomasz Figa <tomasz.figa@gmail.com>
0014
0015 description: |
0016 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
0017 name::
0018 - "fin_pll" - PLL input clock from XXTI
0019
0020 All available clocks are defined as preprocessor macros in
0021 include/dt-bindings/clock/exynos7-clk.h header.
0022
0023 properties:
0024 compatible:
0025 enum:
0026 - samsung,exynos7-clock-topc
0027 - samsung,exynos7-clock-top0
0028 - samsung,exynos7-clock-top1
0029 - samsung,exynos7-clock-ccore
0030 - samsung,exynos7-clock-peric0
0031 - samsung,exynos7-clock-peric1
0032 - samsung,exynos7-clock-peris
0033 - samsung,exynos7-clock-fsys0
0034 - samsung,exynos7-clock-fsys1
0035 - samsung,exynos7-clock-mscl
0036 - samsung,exynos7-clock-aud
0037
0038 clocks:
0039 minItems: 1
0040 maxItems: 13
0041
0042 clock-names:
0043 minItems: 1
0044 maxItems: 13
0045
0046 "#clock-cells":
0047 const: 1
0048
0049 reg:
0050 maxItems: 1
0051
0052 required:
0053 - compatible
0054 - "#clock-cells"
0055 - reg
0056
0057 allOf:
0058 - if:
0059 properties:
0060 compatible:
0061 contains:
0062 const: samsung,exynos7-clock-top0
0063 then:
0064 properties:
0065 clocks:
0066 minItems: 6
0067 maxItems: 6
0068 clock-names:
0069 items:
0070 - const: fin_pll
0071 - const: dout_sclk_bus0_pll
0072 - const: dout_sclk_bus1_pll
0073 - const: dout_sclk_cc_pll
0074 - const: dout_sclk_mfc_pll
0075 - const: dout_sclk_aud_pll
0076 required:
0077 - clock-names
0078 - clocks
0079
0080 - if:
0081 properties:
0082 compatible:
0083 contains:
0084 const: samsung,exynos7-clock-top1
0085 then:
0086 properties:
0087 clocks:
0088 minItems: 5
0089 maxItems: 5
0090 clock-names:
0091 items:
0092 - const: fin_pll
0093 - const: dout_sclk_bus0_pll
0094 - const: dout_sclk_bus1_pll
0095 - const: dout_sclk_cc_pll
0096 - const: dout_sclk_mfc_pll
0097 required:
0098 - clock-names
0099 - clocks
0100
0101 - if:
0102 properties:
0103 compatible:
0104 contains:
0105 const: samsung,exynos7-clock-ccore
0106 then:
0107 properties:
0108 clocks:
0109 minItems: 2
0110 maxItems: 2
0111 clock-names:
0112 items:
0113 - const: fin_pll
0114 - const: dout_aclk_ccore_133
0115 required:
0116 - clock-names
0117 - clocks
0118
0119 - if:
0120 properties:
0121 compatible:
0122 contains:
0123 const: samsung,exynos7-clock-peric0
0124 then:
0125 properties:
0126 clocks:
0127 minItems: 3
0128 maxItems: 3
0129 clock-names:
0130 items:
0131 - const: fin_pll
0132 - const: dout_aclk_peric0_66
0133 - const: sclk_uart0
0134 required:
0135 - clock-names
0136 - clocks
0137
0138 - if:
0139 properties:
0140 compatible:
0141 contains:
0142 const: samsung,exynos7-clock-peric1
0143 then:
0144 properties:
0145 clocks:
0146 minItems: 13
0147 maxItems: 13
0148 clock-names:
0149 items:
0150 - const: fin_pll
0151 - const: dout_aclk_peric1_66
0152 - const: sclk_uart1
0153 - const: sclk_uart2
0154 - const: sclk_uart3
0155 - const: sclk_spi0
0156 - const: sclk_spi1
0157 - const: sclk_spi2
0158 - const: sclk_spi3
0159 - const: sclk_spi4
0160 - const: sclk_i2s1
0161 - const: sclk_pcm1
0162 - const: sclk_spdif
0163 required:
0164 - clock-names
0165 - clocks
0166
0167 - if:
0168 properties:
0169 compatible:
0170 contains:
0171 const: samsung,exynos7-clock-peris
0172 then:
0173 properties:
0174 clocks:
0175 minItems: 2
0176 maxItems: 2
0177 clock-names:
0178 items:
0179 - const: fin_pll
0180 - const: dout_aclk_peris_66
0181 required:
0182 - clock-names
0183 - clocks
0184
0185 - if:
0186 properties:
0187 compatible:
0188 contains:
0189 const: samsung,exynos7-clock-fsys0
0190 then:
0191 properties:
0192 clocks:
0193 minItems: 3
0194 maxItems: 3
0195 clock-names:
0196 items:
0197 - const: fin_pll
0198 - const: dout_aclk_fsys0_200
0199 - const: dout_sclk_mmc2
0200 required:
0201 - clock-names
0202 - clocks
0203
0204 - if:
0205 properties:
0206 compatible:
0207 contains:
0208 const: samsung,exynos7-clock-fsys1
0209 then:
0210 properties:
0211 clocks:
0212 minItems: 7
0213 maxItems: 7
0214 clock-names:
0215 items:
0216 - const: fin_pll
0217 - const: dout_aclk_fsys1_200
0218 - const: dout_sclk_mmc0
0219 - const: dout_sclk_mmc1
0220 - const: dout_sclk_ufsunipro20
0221 - const: dout_sclk_phy_fsys1
0222 - const: dout_sclk_phy_fsys1_26m
0223 required:
0224 - clock-names
0225 - clocks
0226
0227 - if:
0228 properties:
0229 compatible:
0230 contains:
0231 const: samsung,exynos7-clock-aud
0232 then:
0233 properties:
0234 clocks:
0235 minItems: 2
0236 maxItems: 2
0237 clock-names:
0238 items:
0239 - const: fin_pll
0240 - const: fout_aud_pll
0241 required:
0242 - clock-names
0243 - clocks
0244
0245 additionalProperties: false
0246
0247 examples:
0248 - |
0249 #include <dt-bindings/clock/exynos7-clk.h>
0250
0251 fin_pll: clock {
0252 compatible = "fixed-clock";
0253 clock-output-names = "fin_pll";
0254 #clock-cells = <0>;
0255 clock-frequency = <24000000>;
0256 };
0257
0258 clock-controller@105e0000 {
0259 compatible = "samsung,exynos7-clock-top1";
0260 reg = <0x105e0000 0xb000>;
0261 #clock-cells = <1>;
0262 clocks = <&fin_pll>,
0263 <&clock_topc DOUT_SCLK_BUS0_PLL>,
0264 <&clock_topc DOUT_SCLK_BUS1_PLL>,
0265 <&clock_topc DOUT_SCLK_CC_PLL>,
0266 <&clock_topc DOUT_SCLK_MFC_PLL>;
0267 clock-names = "fin_pll",
0268 "dout_sclk_bus0_pll",
0269 "dout_sclk_bus1_pll",
0270 "dout_sclk_cc_pll",
0271 "dout_sclk_mfc_pll";
0272 };
