0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung Exynos SoC Audio SubSystem clock controller
0008
0009 maintainers:
0010 - Chanwoo Choi <cw00.choi@samsung.com>
0011 - Krzysztof Kozlowski <krzk@kernel.org>
0012 - Sylwester Nawrocki <s.nawrocki@samsung.com>
0013 - Tomasz Figa <tomasz.figa@gmail.com>
0014
0015 description: |
0016 All available clocks are defined as preprocessor macros in
0017 include/dt-bindings/clock/exynos-audss-clk.h header.
0018
0019 properties:
0020 compatible:
0021 enum:
0022 - samsung,exynos4210-audss-clock
0023 - samsung,exynos5250-audss-clock
0024 - samsung,exynos5410-audss-clock
0025 - samsung,exynos5420-audss-clock
0026
0027 clocks:
0028 minItems: 2
0029 items:
0030 - description:
0031 Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
0032 used if not specified.
0033 - description:
0034 Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
0035 used if not specified.
0036 - description:
0037 Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if not
0038 specified.
0039 - description:
0040 PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not specified.
0041 - description:
0042 External i2s clock, parent of mout_i2s. "cdclk0" is used if not
0043 specified.
0044
0045 clock-names:
0046 minItems: 2
0047 items:
0048 - const: pll_ref
0049 - const: pll_in
0050 - const: sclk_audio
0051 - const: sclk_pcm_in
0052 - const: cdclk
0053
0054 "#clock-cells":
0055 const: 1
0056
0057 power-domains:
0058 maxItems: 1
0059
0060 reg:
0061 maxItems: 1
0062
0063 required:
0064 - compatible
0065 - clocks
0066 - clock-names
0067 - "#clock-cells"
0068 - reg
0069
0070 additionalProperties: false
0071
0072 examples:
0073 - |
0074 clock-controller@3810000 {
0075 compatible = "samsung,exynos5250-audss-clock";
0076 reg = <0x03810000 0x0c>;
0077 #clock-cells = <1>;
0078 clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, <&ext_i2s_clk>;
0079 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
0080 };
