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0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: Rockchip RV1108 Clock and Reset Unit (CRU)
0008 
0009 maintainers:
0010   - Elaine Zhang <zhangqing@rock-chips.com>
0011   - Heiko Stuebner <heiko@sntech.de>
0012 
0013 description: |
0014   The RV1108 clock controller generates and supplies clocks to various
0015   controllers within the SoC and also implements a reset controller for SoC
0016   peripherals.
0017   Each clock is assigned an identifier and client nodes can use this identifier
0018   to specify the clock which they consume. All available clocks are defined as
0019   preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
0020   used in device tree sources. Similar macros exist for the reset sources in
0021   these files.
0022   There are several clocks that are generated outside the SoC. It is expected
0023   that they are defined using standard clock bindings with following
0024   clock-output-names:
0025     - "xin24m"   - crystal input                              - required
0026     - "ext_vip"  - external VIP clock                         - optional
0027     - "ext_i2s"  - external I2S clock                         - optional
0028     - "ext_gmac" - external GMAC clock                        - optional
0029     - "hdmiphy"  - external clock input derived from HDMI PHY - optional
0030     - "usbphy"   - external clock input derived from USB PHY  - optional
0031 
0032 properties:
0033   compatible:
0034     enum:
0035       - rockchip,rv1108-cru
0036 
0037   reg:
0038     maxItems: 1
0039 
0040   "#clock-cells":
0041     const: 1
0042 
0043   "#reset-cells":
0044     const: 1
0045 
0046   clocks:
0047     maxItems: 1
0048 
0049   clock-names:
0050     const: xin24m
0051 
0052   rockchip,grf:
0053     $ref: /schemas/types.yaml#/definitions/phandle
0054     description:
0055       Phandle to the syscon managing the "general register files" (GRF),
0056       if missing pll rates are not changeable, due to the missing pll
0057       lock status.
0058 
0059 required:
0060   - compatible
0061   - reg
0062   - "#clock-cells"
0063   - "#reset-cells"
0064 
0065 additionalProperties: false
0066 
0067 examples:
0068   - |
0069     cru: clock-controller@20200000 {
0070       compatible = "rockchip,rv1108-cru";
0071       reg = <0x20200000 0x1000>;
0072       rockchip,grf = <&grf>;
0073       #clock-cells = <1>;
0074       #reset-cells = <1>;
0075     };