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0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: Rockchip RK3399 Clock and Reset Unit
0008 
0009 maintainers:
0010   - Elaine Zhang <zhangqing@rock-chips.com>
0011   - Heiko Stuebner <heiko@sntech.de>
0012 
0013 description: |
0014   The RK3399 clock controller generates and supplies clock to various
0015   controllers within the SoC and also implements a reset controller for SoC
0016   peripherals.
0017   Each clock is assigned an identifier and client nodes can use this identifier
0018   to specify the clock which they consume. All available clocks are defined as
0019   preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
0020   used in device tree sources. Similar macros exist for the reset sources in
0021   these files.
0022   There are several clocks that are generated outside the SoC. It is expected
0023   that they are defined using standard clock bindings with following
0024   clock-output-names:
0025     - "xin24m"           - crystal input                          - required,
0026     - "xin32k"           - rtc clock                              - optional,
0027     - "clkin_gmac"       - external GMAC clock                    - optional,
0028     - "clkin_i2s"        - external I2S clock                     - optional,
0029     - "pclkin_cif"       - external ISP clock                     - optional,
0030     - "clk_usbphy0_480m" - output clock of the pll in the usbphy0
0031     - "clk_usbphy1_480m" - output clock of the pll in the usbphy1
0032 
0033 properties:
0034   compatible:
0035     enum:
0036       - rockchip,rk3399-pmucru
0037       - rockchip,rk3399-cru
0038 
0039   reg:
0040     maxItems: 1
0041 
0042   "#clock-cells":
0043     const: 1
0044 
0045   "#reset-cells":
0046     const: 1
0047 
0048   clocks:
0049     maxItems: 1
0050 
0051   clock-names:
0052     const: xin24m
0053 
0054   rockchip,grf:
0055     $ref: /schemas/types.yaml#/definitions/phandle
0056     description:
0057       Phandle to the syscon managing the "general register files". It is used
0058       for GRF muxes, if missing any muxes present in the GRF will not be
0059       available.
0060 
0061 required:
0062   - compatible
0063   - reg
0064   - "#clock-cells"
0065   - "#reset-cells"
0066 
0067 additionalProperties: false
0068 
0069 examples:
0070   - |
0071     pmucru: clock-controller@ff750000 {
0072       compatible = "rockchip,rk3399-pmucru";
0073       reg = <0xff750000 0x1000>;
0074       #clock-cells = <1>;
0075       #reset-cells = <1>;
0076     };
0077   - |
0078     cru: clock-controller@ff760000 {
0079       compatible = "rockchip,rk3399-cru";
0080       reg = <0xff760000 0x1000>;
0081       #clock-cells = <1>;
0082       #reset-cells = <1>;
0083     };