bindings/clock/rockchip%2Crk3288-cru.yaml

0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip RK3288 Clock and Reset Unit (CRU)
0008
0009 maintainers:
0010   - Elaine Zhang <zhangqing@rock-chips.com>
0011   - Heiko Stuebner <heiko@sntech.de>
0012
0013 description: |
0014   The RK3288 clock controller generates and supplies clocks to various
0015   controllers within the SoC and also implements a reset controller for SoC
0016   peripherals.
0017
0018   A revision of this SoC is available: rk3288w. The clock tree is a bit
0019   different so another dt-compatible is available. Noticed that it is only
0020   setting the difference but there is no automatic revision detection. This
0021   should be performed by boot loaders.
0022
0023   Each clock is assigned an identifier and client nodes can use this identifier
0024   to specify the clock which they consume. All available clocks are defined as
0025   preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
0026   used in device tree sources. Similar macros exist for the reset sources in
0027   these files.
0028
0029   There are several clocks that are generated outside the SoC. It is expected
0030   that they are defined using standard clock bindings with following
0031   clock-output-names:
0032     - "xin24m"      - crystal input               - required,
0033     - "xin32k"      - rtc clock                   - optional,
0034     - "ext_i2s"     - external I2S clock          - optional,
0035     - "ext_hsadc"   - external HSADC clock        - optional,
0036     - "ext_edp_24m" - external display port clock - optional,
0037     - "ext_vip"     - external VIP clock          - optional,
0038     - "ext_isp"     - external ISP clock          - optional,
0039     - "ext_jtag"    - external JTAG clock         - optional
0040
0041 properties:
0042   compatible:
0043     enum:
0044       - rockchip,rk3288-cru
0045       - rockchip,rk3288w-cru
0046
0047   reg:
0048     maxItems: 1
0049
0050   "#clock-cells":
0051     const: 1
0052
0053   "#reset-cells":
0054     const: 1
0055
0056   clocks:
0057     maxItems: 1
0058
0059   clock-names:
0060     const: xin24m
0061
0062   rockchip,grf:
0063     $ref: /schemas/types.yaml#/definitions/phandle
0064     description:
0065       Phandle to the syscon managing the "general register files" (GRF),
0066       if missing pll rates are not changeable, due to the missing pll
0067       lock status.
0068
0069 required:
0070   - compatible
0071   - reg
0072   - "#clock-cells"
0073   - "#reset-cells"
0074
0075 additionalProperties: false
0076
0077 examples:
0078   - |
0079     cru: clock-controller@ff760000 {
0080       compatible = "rockchip,rk3288-cru";
0081       reg = <0xff760000 0x1000>;
0082       rockchip,grf = <&grf>;
0083       #clock-cells = <1>;
0084       #reset-cells = <1>;
0085     };