bindings/clock/rockchip%2Cpx30-cru.yaml

0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip PX30 Clock and Reset Unit (CRU)
0008
0009 maintainers:
0010   - Elaine Zhang <zhangqing@rock-chips.com>
0011   - Heiko Stuebner <heiko@sntech.de>
0012
0013 description: |
0014   The PX30 clock controller generates and supplies clocks to various
0015   controllers within the SoC and also implements a reset controller for SoC
0016   peripherals.
0017   Each clock is assigned an identifier and client nodes can use this identifier
0018   to specify the clock which they consume. All available clocks are defined as
0019   preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
0020   used in device tree sources. Similar macros exist for the reset sources in
0021   these files.
0022   There are several clocks that are generated outside the SoC. It is expected
0023   that they are defined using standard clock bindings with following
0024   clock-output-names:
0025     - "xin24m"     - crystal input       - required
0026     - "xin32k"     - rtc clock           - optional
0027     - "i2sx_clkin" - external I2S clock  - optional
0028     - "gmac_clkin" - external GMAC clock - optional
0029
0030 properties:
0031   compatible:
0032     enum:
0033       - rockchip,px30-cru
0034       - rockchip,px30-pmucru
0035
0036   reg:
0037     maxItems: 1
0038
0039   "#clock-cells":
0040     const: 1
0041
0042   "#reset-cells":
0043     const: 1
0044
0045   clocks:
0046     minItems: 1
0047     items:
0048       - description: Clock for both PMUCRU and CRU
0049       - description: Clock for CRU (sourced from PMUCRU)
0050
0051   clock-names:
0052     minItems: 1
0053     items:
0054       - const: xin24m
0055       - const: gpll
0056
0057   rockchip,grf:
0058     $ref: /schemas/types.yaml#/definitions/phandle
0059     description:
0060       Phandle to the syscon managing the "general register files" (GRF),
0061       if missing pll rates are not changeable, due to the missing pll
0062       lock status.
0063
0064 required:
0065   - compatible
0066   - reg
0067   - clocks
0068   - clock-names
0069   - "#clock-cells"
0070   - "#reset-cells"
0071
0072 allOf:
0073   - if:
0074       properties:
0075         compatible:
0076           contains:
0077             const: rockchip,px30-cru
0078
0079     then:
0080       properties:
0081         clocks:
0082           minItems: 2
0083
0084         clock-names:
0085           minItems: 2
0086
0087     else:
0088       properties:
0089         clocks:
0090           maxItems: 1
0091
0092         clock-names:
0093           maxItems: 1
0094
0095 additionalProperties: false
0096
0097 examples:
0098   - |
0099     #include <dt-bindings/clock/px30-cru.h>
0100
0101     pmucru: clock-controller@ff2bc000 {
0102       compatible = "rockchip,px30-pmucru";
0103       reg = <0xff2bc000 0x1000>;
0104       clocks = <&xin24m>;
0105       clock-names = "xin24m";
0106       rockchip,grf = <&grf>;
0107       #clock-cells = <1>;
0108       #reset-cells = <1>;
0109     };
0110
0111     cru: clock-controller@ff2b0000 {
0112       compatible = "rockchip,px30-cru";
0113       reg = <0xff2b0000 0x1000>;
0114       clocks = <&xin24m>, <&pmucru PLL_GPLL>;
0115       clock-names = "xin24m", "gpll";
0116       rockchip,grf = <&grf>;
0117       #clock-cells = <1>;
0118       #reset-cells = <1>;
0119     };