0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
0008
0009 maintainers:
0010 - Geert Uytterhoeven <geert+renesas@glider.be>
0011
0012 description: |
0013 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
0014 Standby Mode share the same register block. On RZ/V2M, the functionality is
0015 similar, but does not have Clock Monitor Registers.
0016
0017 They provide the following functionalities:
0018 - The CPG block generates various core clocks,
0019 - The Module Standby Mode block provides two functions:
0020 1. Module Standby, providing a Clock Domain to control the clock supply
0021 to individual SoC devices,
0022 2. Reset Control, to perform a software reset of individual SoC devices.
0023
0024 properties:
0025 compatible:
0026 enum:
0027 - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
0028 - renesas,r9a07g044-cpg # RZ/G2{L,LC}
0029 - renesas,r9a07g054-cpg # RZ/V2L
0030 - renesas,r9a09g011-cpg # RZ/V2M
0031
0032 reg:
0033 maxItems: 1
0034
0035 clocks:
0036 maxItems: 1
0037
0038 clock-names:
0039 description:
0040 Clock source to CPG can be either from external clock input (EXCLK) or
0041 crystal oscillator (XIN/XOUT).
0042 const: extal
0043
0044 '#clock-cells':
0045 description: |
0046 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
0047 and a core clock reference, as defined in
0048 <dt-bindings/clock/r9a0*-cpg.h>,
0049 - For module clocks, the two clock specifier cells must be "CPG_MOD" and
0050 a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
0051 const: 2
0052
0053 '#power-domain-cells':
0054 description:
0055 SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
0056 can be power-managed through Module Standby should refer to the CPG device
0057 node in their "power-domains" property, as documented by the generic PM
0058 Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
0059 const: 0
0060
0061 '#reset-cells':
0062 description:
0063 The single reset specifier cell must be the module number, as defined in
0064 <dt-bindings/clock/r9a0*-cpg.h>.
0065 const: 1
0066
0067 required:
0068 - compatible
0069 - reg
0070 - clocks
0071 - clock-names
0072 - '#clock-cells'
0073 - '#power-domain-cells'
0074 - '#reset-cells'
0075
0076 additionalProperties: false
0077
0078 examples:
0079 - |
0080 cpg: clock-controller@11010000 {
0081 compatible = "renesas,r9a07g044-cpg";
0082 reg = <0x11010000 0x10000>;
0083 clocks = <&extal_clk>;
0084 clock-names = "extal";
0085 #clock-cells = <2>;
0086 #power-domain-cells = <0>;
0087 #reset-cells = <1>;
0088 };
