0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas EMMA Mobile EV2 System Management Unit
0008
0009 maintainers:
0010 - Geert Uytterhoeven <geert+renesas@glider.be>
0011 - Magnus Damm <magnus.damm@gmail.com>
0012
0013 description: |
0014 The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
0015 This is not a clock provider, but clocks under SMU depend on it.
0016
0017 properties:
0018 compatible:
0019 const: renesas,emev2-smu
0020
0021 reg:
0022 maxItems: 1
0023
0024 '#address-cells':
0025 const: 2
0026
0027 '#size-cells':
0028 const: 0
0029
0030 required:
0031 - compatible
0032 - reg
0033 - '#address-cells'
0034 - '#size-cells'
0035
0036 patternProperties:
0037 ".*sclkdiv@.*":
0038 type: object
0039
0040 description: |
0041 Function block with an input mux and a divider, which corresponds to
0042 "Serial clock generator" in fig. "Clock System Overview" of the manual,
0043 and "xxx frequency division setting register" (XXXCLKDIV) registers.
0044 This makes internal (neither input nor output) clock that is provided
0045 to input of xxxGCLK block.
0046
0047 properties:
0048 compatible:
0049 const: renesas,emev2-smu-clkdiv
0050
0051 reg:
0052 maxItems: 1
0053 description:
0054 Byte offset from SMU base and Bit position in the register.
0055
0056 clocks:
0057 minItems: 1
0058 maxItems: 4
0059
0060 '#clock-cells':
0061 const: 0
0062
0063 required:
0064 - compatible
0065 - reg
0066 - clocks
0067 - '#clock-cells'
0068
0069 additionalProperties: false
0070
0071 ".*sclk@.*":
0072 type: object
0073
0074 description: |
0075 Clock gating node shown as "Clock stop processing block" in the
0076 fig. "Clock System Overview" of the manual.
0077 Registers are "xxx clock gate control register" (XXXGCLKCTRL).
0078
0079 properties:
0080 compatible:
0081 const: renesas,emev2-smu-gclk
0082
0083 reg:
0084 maxItems: 1
0085 description:
0086 Byte offset from SMU base and Bit position in the register.
0087
0088 clocks:
0089 maxItems: 1
0090
0091 '#clock-cells':
0092 const: 0
0093
0094 required:
0095 - compatible
0096 - reg
0097 - clocks
0098 - '#clock-cells'
0099
0100 additionalProperties: false
0101
0102 additionalProperties: true
0103
0104 examples:
0105 - |
0106 // Example of clock-tree description:
0107 //
0108 // This describes a clock path in the clock tree
0109 // c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
0110 clocks@e0110000 {
0111 compatible = "renesas,emev2-smu";
0112 reg = <0xe0110000 0x10000>;
0113 #address-cells = <2>;
0114 #size-cells = <0>;
0115
0116 c32ki: c32ki {
0117 compatible = "fixed-clock";
0118 clock-frequency = <32768>;
0119 #clock-cells = <0>;
0120 };
0121 pll3_fo: pll3_fo {
0122 compatible = "fixed-factor-clock";
0123 clocks = <&c32ki>;
0124 clock-div = <1>;
0125 clock-mult = <7000>;
0126 #clock-cells = <0>;
0127 };
0128 usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
0129 compatible = "renesas,emev2-smu-clkdiv";
0130 reg = <0x610 0>;
0131 clocks = <&pll3_fo>;
0132 #clock-cells = <0>;
0133 };
0134 usia_u0_sclk: usia_u0_sclk@4a0,1 {
0135 compatible = "renesas,emev2-smu-gclk";
0136 reg = <0x4a0 1>;
0137 clocks = <&usia_u0_sclkdiv>;
0138 #clock-cells = <0>;
0139 };
0140 };
