0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
0008
0009 maintainers:
0010 - Geert Uytterhoeven <geert+renesas@glider.be>
0011
0012 description:
0013 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
0014 organized in groups of up to 32 gates.
0015
0016 This device tree binding describes a single 32 gate clocks group per node.
0017 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
0018 and the clock index in the group, from 0 to 31.
0019
0020 properties:
0021 compatible:
0022 items:
0023 - enum:
0024 - renesas,r7s72100-mstp-clocks # RZ/A1
0025 - renesas,r8a73a4-mstp-clocks # R-Mobile APE6
0026 - renesas,r8a7740-mstp-clocks # R-Mobile A1
0027 - renesas,r8a7778-mstp-clocks # R-Car M1
0028 - renesas,r8a7779-mstp-clocks # R-Car H1
0029 - renesas,sh73a0-mstp-clocks # SH-Mobile AG5
0030 - const: renesas,cpg-mstp-clocks
0031
0032 reg:
0033 minItems: 1
0034 items:
0035 - description: Module Stop Control Register (MSTPCR)
0036 - description: Module Stop Status Register (MSTPSR)
0037
0038 clocks:
0039 minItems: 1
0040 maxItems: 32
0041
0042 '#clock-cells':
0043 const: 1
0044
0045 clock-indices:
0046 minItems: 1
0047 maxItems: 32
0048
0049 clock-output-names:
0050 minItems: 1
0051 maxItems: 32
0052
0053 required:
0054 - compatible
0055 - reg
0056 - clocks
0057 - '#clock-cells'
0058 - clock-indices
0059 - clock-output-names
0060
0061 additionalProperties: false
0062
0063 examples:
0064 - |
0065 #include <dt-bindings/clock/r8a73a4-clock.h>
0066 mstp2_clks: mstp2_clks@e6150138 {
0067 compatible = "renesas,r8a73a4-mstp-clocks",
0068 "renesas,cpg-mstp-clocks";
0069 reg = <0xe6150138 4>, <0xe6150040 4>;
0070 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
0071 <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
0072 #clock-cells = <1>;
0073 clock-indices = <
0074 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
0075 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
0076 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
0077 R8A73A4_CLK_DMAC
0078 >;
0079 clock-output-names =
0080 "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3",
0081 "dmac";
0082 };
