0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Renesas Clock Pulse Generator / Module Standby and Software Reset
0008
0009 maintainers:
0010 - Geert Uytterhoeven <geert+renesas@glider.be>
0011
0012 description: |
0013 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
0014 and MSSR (Module Standby and Software Reset) blocks are intimately connected,
0015 and share the same register block.
0016
0017 They provide the following functionalities:
0018 - The CPG block generates various core clocks,
0019 - The MSSR block provides two functions:
0020 1. Module Standby, providing a Clock Domain to control the clock supply
0021 to individual SoC devices,
0022 2. Reset Control, to perform a software reset of individual SoC devices.
0023
0024 properties:
0025 compatible:
0026 enum:
0027 - renesas,r7s9210-cpg-mssr # RZ/A2
0028 - renesas,r8a7742-cpg-mssr # RZ/G1H
0029 - renesas,r8a7743-cpg-mssr # RZ/G1M
0030 - renesas,r8a7744-cpg-mssr # RZ/G1N
0031 - renesas,r8a7745-cpg-mssr # RZ/G1E
0032 - renesas,r8a77470-cpg-mssr # RZ/G1C
0033 - renesas,r8a774a1-cpg-mssr # RZ/G2M
0034 - renesas,r8a774b1-cpg-mssr # RZ/G2N
0035 - renesas,r8a774c0-cpg-mssr # RZ/G2E
0036 - renesas,r8a774e1-cpg-mssr # RZ/G2H
0037 - renesas,r8a7790-cpg-mssr # R-Car H2
0038 - renesas,r8a7791-cpg-mssr # R-Car M2-W
0039 - renesas,r8a7792-cpg-mssr # R-Car V2H
0040 - renesas,r8a7793-cpg-mssr # R-Car M2-N
0041 - renesas,r8a7794-cpg-mssr # R-Car E2
0042 - renesas,r8a7795-cpg-mssr # R-Car H3
0043 - renesas,r8a7796-cpg-mssr # R-Car M3-W
0044 - renesas,r8a77961-cpg-mssr # R-Car M3-W+
0045 - renesas,r8a77965-cpg-mssr # R-Car M3-N
0046 - renesas,r8a77970-cpg-mssr # R-Car V3M
0047 - renesas,r8a77980-cpg-mssr # R-Car V3H
0048 - renesas,r8a77990-cpg-mssr # R-Car E3
0049 - renesas,r8a77995-cpg-mssr # R-Car D3
0050 - renesas,r8a779a0-cpg-mssr # R-Car V3U
0051 - renesas,r8a779f0-cpg-mssr # R-Car S4-8
0052 - renesas,r8a779g0-cpg-mssr # R-Car V4H
0053
0054 reg:
0055 maxItems: 1
0056
0057 clocks:
0058 minItems: 1
0059 maxItems: 2
0060
0061 clock-names:
0062 minItems: 1
0063 maxItems: 2
0064 items:
0065 enum:
0066 - extal # All
0067 - extalr # Most R-Car Gen3 and RZ/G2
0068 - usb_extal # Most R-Car Gen2 and RZ/G1
0069
0070 '#clock-cells':
0071 description: |
0072 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
0073 and a core clock reference, as defined in
0074 <dt-bindings/clock/*-cpg-mssr.h>
0075 - For module clocks, the two clock specifier cells must be "CPG_MOD" and
0076 a module number, as defined in the datasheet.
0077 const: 2
0078
0079 '#power-domain-cells':
0080 description:
0081 SoC devices that are part of the CPG/MSSR Clock Domain and can be
0082 power-managed through Module Standby should refer to the CPG device node
0083 in their "power-domains" property, as documented by the generic PM Domain
0084 bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
0085 const: 0
0086
0087 '#reset-cells':
0088 description:
0089 The single reset specifier cell must be the module number, as defined in
0090 the datasheet.
0091 const: 1
0092
0093 if:
0094 not:
0095 properties:
0096 compatible:
0097 items:
0098 enum:
0099 - renesas,r7s9210-cpg-mssr
0100 then:
0101 required:
0102 - '#reset-cells'
0103
0104 required:
0105 - compatible
0106 - reg
0107 - clocks
0108 - clock-names
0109 - '#clock-cells'
0110 - '#power-domain-cells'
0111
0112 additionalProperties: false
0113
0114 examples:
0115 - |
0116 cpg: clock-controller@e6150000 {
0117 compatible = "renesas,r8a7795-cpg-mssr";
0118 reg = <0xe6150000 0x1000>;
0119 clocks = <&extal_clk>, <&extalr_clk>;
0120 clock-names = "extal", "extalr";
0121 #clock-cells = <2>;
0122 #power-domain-cells = <0>;
0123 #reset-cells = <1>;
0124 };
