0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas CPG DIV6 Clock
0008
0009 maintainers:
0010 - Geert Uytterhoeven <geert+renesas@glider.be>
0011
0012 description:
0013 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
0014 Generator (CPG). Their clock input is divided by a configurable factor from 1
0015 to 64.
0016
0017 properties:
0018 compatible:
0019 items:
0020 - enum:
0021 - renesas,r8a73a4-div6-clock # R-Mobile APE6
0022 - renesas,r8a7740-div6-clock # R-Mobile A1
0023 - renesas,sh73a0-div6-clock # SH-Mobile AG5
0024 - const: renesas,cpg-div6-clock
0025
0026 reg:
0027 maxItems: 1
0028
0029 clocks:
0030 oneOf:
0031 - maxItems: 1
0032 - maxItems: 4
0033 - maxItems: 8
0034 description:
0035 For clocks with multiple parents, invalid settings must be specified as
0036 "<0>".
0037
0038 '#clock-cells':
0039 const: 0
0040
0041 clock-output-names: true
0042
0043 required:
0044 - compatible
0045 - reg
0046 - clocks
0047 - '#clock-cells'
0048
0049 additionalProperties: false
0050
0051 examples:
0052 - |
0053 #include <dt-bindings/clock/r8a73a4-clock.h>
0054
0055 cpg_clocks: cpg_clocks@e6150000 {
0056 compatible = "renesas,r8a73a4-cpg-clocks";
0057 reg = <0xe6150000 0x10000>;
0058 clocks = <&extal1_clk>, <&extal2_clk>;
0059 #clock-cells = <1>;
0060 clock-output-names = "main", "pll0", "pll1", "pll2",
0061 "pll2s", "pll2h", "z", "z2",
0062 "i", "m3", "b", "m1", "m2",
0063 "zx", "zs", "hp";
0064 };
0065
0066 sdhi2_clk: sdhi2_clk@e615007c {
0067 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0068 reg = <0xe615007c 4>;
0069 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
0070 <&extal2_clk>;
0071 #clock-cells = <0>;
0072 };
