0001 * Clock Block on Freescale QorIQ Platforms
0002
0003 Freescale QorIQ chips take primary clocking input from the external
0004 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
0005 multiple phase locked loops (PLL) to create a variety of frequencies
0006 which can then be passed to a variety of internal logic, including
0007 cores and peripheral IP blocks.
0008 Please refer to the Reference Manual for details.
0009
0010 All references to "1.0" and "2.0" refer to the QorIQ chassis version to
0011 which the chip complies.
0012
0013 Chassis Version Example Chips
0014 --------------- -------------
0015 1.0 p4080, p5020, p5040
0016 2.0 t4240, b4860
0017
0018 1. Clock Block Binding
0019
0020 Required properties:
0021 - compatible: Should contain a chip-specific clock block compatible
0022 string and (if applicable) may contain a chassis-version clock
0023 compatible string.
0024
0025 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
0026 * "fsl,p2041-clockgen"
0027 * "fsl,p3041-clockgen"
0028 * "fsl,p4080-clockgen"
0029 * "fsl,p5020-clockgen"
0030 * "fsl,p5040-clockgen"
0031 * "fsl,t1023-clockgen"
0032 * "fsl,t1024-clockgen"
0033 * "fsl,t1040-clockgen"
0034 * "fsl,t1042-clockgen"
0035 * "fsl,t2080-clockgen"
0036 * "fsl,t2081-clockgen"
0037 * "fsl,t4240-clockgen"
0038 * "fsl,b4420-clockgen"
0039 * "fsl,b4860-clockgen"
0040 * "fsl,ls1012a-clockgen"
0041 * "fsl,ls1021a-clockgen"
0042 * "fsl,ls1028a-clockgen"
0043 * "fsl,ls1043a-clockgen"
0044 * "fsl,ls1046a-clockgen"
0045 * "fsl,ls1088a-clockgen"
0046 * "fsl,ls2080a-clockgen"
0047 * "fsl,lx2160a-clockgen"
0048 Chassis-version clock strings include:
0049 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
0050 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
0051 - reg: Describes the address of the device's resources within the
0052 address space defined by its parent bus, and resource zero
0053 represents the clock register set
0054
0055 Optional properties:
0056 - ranges: Allows valid translation between child's address space and
0057 parent's. Must be present if the device has sub-nodes.
0058 - #address-cells: Specifies the number of cells used to represent
0059 physical base addresses. Must be present if the device has
0060 sub-nodes and set to 1 if present
0061 - #size-cells: Specifies the number of cells used to represent
0062 the size of an address. Must be present if the device has
0063 sub-nodes and set to 1 if present
0064 - clock-frequency: Input system clock frequency (SYSCLK)
0065 - clocks: If clock-frequency is not specified, sysclk may be provided
0066 as an input clock. Either clock-frequency or clocks must be
0067 provided.
0068 A second input clock, called "coreclk", may be provided if
0069 core PLLs are based on a different input clock from the
0070 platform PLL.
0071 - clock-names: Required if a coreclk is present. Valid names are
0072 "sysclk" and "coreclk".
0073
0074 2. Clock Provider
0075
0076 The clockgen node should act as a clock provider, though in older device
0077 trees the children of the clockgen node are the clock providers.
0078
0079 When the clockgen node is a clock provider, #clock-cells = <2>.
0080 The first cell of the clock specifier is the clock type, and the
0081 second cell is the clock index for the specified type.
0082
0083 Type# Name Index Cell
0084 0 sysclk must be 0
0085 1 cmux index (n in CLKCnCSR)
0086 2 hwaccel index (n in CLKCGnHWACSR)
0087 3 fman 0 for fm1, 1 for fm2
0088 4 platform pll n=pll/(n+1). For example, when n=1,
0089 that means output_freq=PLL_freq/2.
0090 5 coreclk must be 0
0091
0092 3. Example
0093
0094 clockgen: global-utilities@e1000 {
0095 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
0096 clock-frequency = <133333333>;
0097 reg = <0xe1000 0x1000>;
0098 #clock-cells = <2>;
0099 };
0100
0101 fman@400000 {
0102 ...
0103 clocks = <&clockgen 3 0>;
0104 ...
0105 };
0106 }
0107 4. Legacy Child Nodes
0108
0109 NOTE: These nodes are deprecated. Kernels should continue to support
0110 device trees with these nodes, but new device trees should not use them.
0111
0112 Most of the bindings are from the common clock binding[1].
0113 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0114
0115 Required properties:
0116 - compatible : Should include one of the following:
0117 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
0118 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
0119 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
0120 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
0121 * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
0122 It takes parent's clock-frequency as its clock.
0123 * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
0124 It takes parent's clock-frequency as its clock.
0125 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
0126 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
0127 - #clock-cells: From common clock binding. The number of cells in a
0128 clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
0129 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
0130 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
0131 clock-specifier cell may take the following values:
0132 * 0 - equal to the PLL frequency
0133 * 1 - equal to the PLL frequency divided by 2
0134 * 2 - equal to the PLL frequency divided by 4
0135
0136 Recommended properties:
0137 - clocks: Should be the phandle of input parent clock
0138 - clock-names: From common clock binding, indicates the clock name
0139 - clock-output-names: From common clock binding, indicates the names of
0140 output clocks
0141 - reg: Should be the offset and length of clock block base address.
0142 The length should be 4.
0143
0144 Legacy Example:
0145 / {
0146 clockgen: global-utilities@e1000 {
0147 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
0148 ranges = <0x0 0xe1000 0x1000>;
0149 clock-frequency = <133333333>;
0150 reg = <0xe1000 0x1000>;
0151 #address-cells = <1>;
0152 #size-cells = <1>;
0153
0154 sysclk: sysclk {
0155 #clock-cells = <0>;
0156 compatible = "fsl,qoriq-sysclk-1.0";
0157 clock-output-names = "sysclk";
0158 };
0159
0160 pll0: pll0@800 {
0161 #clock-cells = <1>;
0162 reg = <0x800 0x4>;
0163 compatible = "fsl,qoriq-core-pll-1.0";
0164 clocks = <&sysclk>;
0165 clock-output-names = "pll0", "pll0-div2";
0166 };
0167
0168 pll1: pll1@820 {
0169 #clock-cells = <1>;
0170 reg = <0x820 0x4>;
0171 compatible = "fsl,qoriq-core-pll-1.0";
0172 clocks = <&sysclk>;
0173 clock-output-names = "pll1", "pll1-div2";
0174 };
0175
0176 mux0: mux0@0 {
0177 #clock-cells = <0>;
0178 reg = <0x0 0x4>;
0179 compatible = "fsl,qoriq-core-mux-1.0";
0180 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
0181 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
0182 clock-output-names = "cmux0";
0183 };
0184
0185 mux1: mux1@20 {
0186 #clock-cells = <0>;
0187 reg = <0x20 0x4>;
0188 compatible = "fsl,qoriq-core-mux-1.0";
0189 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
0190 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
0191 clock-output-names = "cmux1";
0192 };
0193
0194 platform-pll: platform-pll@c00 {
0195 #clock-cells = <1>;
0196 reg = <0xc00 0x4>;
0197 compatible = "fsl,qoriq-platform-pll-1.0";
0198 clocks = <&sysclk>;
0199 clock-output-names = "platform-pll", "platform-pll-div2";
0200 };
0201 };
0202 };
0203
0204 Example for legacy clock consumer:
0205
0206 / {
0207 cpu0: PowerPC,e5500@0 {
0208 ...
0209 clocks = <&mux0>;
0210 ...
0211 };
0212 };
