0001 Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)
0002
0003 clkdiv configures the clock frequency of a set of outputs on the PMIC.
0004 These clocks are typically wired through alternate functions on
0005 gpio pins.
0006
0007 =======================
0008 Properties
0009 =======================
0010
0011 - compatible
0012 Usage: required
0013 Value type: <string>
0014 Definition: must be "qcom,spmi-clkdiv".
0015
0016 - reg
0017 Usage: required
0018 Value type: <prop-encoded-array>
0019 Definition: base address of CLKDIV peripherals.
0020
0021 - qcom,num-clkdivs
0022 Usage: required
0023 Value type: <u32>
0024 Definition: number of CLKDIV peripherals.
0025
0026 - clocks:
0027 Usage: required
0028 Value type: <prop-encoded-array>
0029 Definition: reference to the xo clock.
0030
0031 - clock-names:
0032 Usage: required
0033 Value type: <stringlist>
0034 Definition: must be "xo".
0035
0036 - #clock-cells:
0037 Usage: required
0038 Value type: <u32>
0039 Definition: shall contain 1.
0040
0041 =======
0042 Example
0043 =======
0044
0045 pm8998_clk_divs: clock-controller@5b00 {
0046 compatible = "qcom,spmi-clkdiv";
0047 reg = <0x5b00>;
0048 #clock-cells = <1>;
0049 qcom,num-clkdivs = <3>;
0050 clocks = <&xo_board>;
0051 clock-names = "xo";
0052
0053 assigned-clocks = <&pm8998_clk_divs 1>,
0054 <&pm8998_clk_divs 2>,
0055 <&pm8998_clk_divs 3>;
0056 assigned-clock-rates = <9600000>,
0057 <9600000>,
0058 <9600000>;
0059 };
