0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display Clock & Reset Controller Binding for SDM845
0008
0009 maintainers:
0010 - Taniya Das <tdas@codeaurora.org>
0011
0012 description: |
0013 Qualcomm display clock control module which supports the clocks, resets and
0014 power domains on SDM845.
0015
0016 See also dt-bindings/clock/qcom,dispcc-sdm845.h.
0017
0018 properties:
0019 compatible:
0020 const: qcom,sdm845-dispcc
0021
0022 # NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
0023 # The code had to use hardcoded mechanisms to find the input clocks.
0024 # New dts files should have these clocks.
0025 clocks:
0026 items:
0027 - description: Board XO source
0028 - description: GPLL0 source from GCC
0029 - description: GPLL0 div source from GCC
0030 - description: Byte clock from DSI PHY0
0031 - description: Pixel clock from DSI PHY0
0032 - description: Byte clock from DSI PHY1
0033 - description: Pixel clock from DSI PHY1
0034 - description: Link clock from DP PHY
0035 - description: VCO DIV clock from DP PHY
0036
0037 clock-names:
0038 items:
0039 - const: bi_tcxo
0040 - const: gcc_disp_gpll0_clk_src
0041 - const: gcc_disp_gpll0_div_clk_src
0042 - const: dsi0_phy_pll_out_byteclk
0043 - const: dsi0_phy_pll_out_dsiclk
0044 - const: dsi1_phy_pll_out_byteclk
0045 - const: dsi1_phy_pll_out_dsiclk
0046 - const: dp_link_clk_divsel_ten
0047 - const: dp_vco_divided_clk_src_mux
0048
0049 '#clock-cells':
0050 const: 1
0051
0052 '#reset-cells':
0053 const: 1
0054
0055 '#power-domain-cells':
0056 const: 1
0057
0058 reg:
0059 maxItems: 1
0060
0061 required:
0062 - compatible
0063 - reg
0064 - clocks
0065 - clock-names
0066 - '#clock-cells'
0067 - '#reset-cells'
0068 - '#power-domain-cells'
0069
0070 additionalProperties: false
0071
0072 examples:
0073 - |
0074 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
0075 #include <dt-bindings/clock/qcom,rpmh.h>
0076 clock-controller@af00000 {
0077 compatible = "qcom,sdm845-dispcc";
0078 reg = <0x0af00000 0x10000>;
0079 clocks = <&rpmhcc RPMH_CXO_CLK>,
0080 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
0081 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
0082 <&dsi0_phy 0>,
0083 <&dsi0_phy 1>,
0084 <&dsi1_phy 0>,
0085 <&dsi1_phy 1>,
0086 <&dp_phy 0>,
0087 <&dp_phy 1>;
0088 clock-names = "bi_tcxo",
0089 "gcc_disp_gpll0_clk_src",
0090 "gcc_disp_gpll0_div_clk_src",
0091 "dsi0_phy_pll_out_byteclk",
0092 "dsi0_phy_pll_out_dsiclk",
0093 "dsi1_phy_pll_out_byteclk",
0094 "dsi1_phy_pll_out_dsiclk",
0095 "dp_link_clk_divsel_ten",
0096 "dp_vco_divided_clk_src_mux";
0097 #clock-cells = <1>;
0098 #reset-cells = <1>;
0099 #power-domain-cells = <1>;
0100 };
0101 ...
